In this paper the design of CPU with Cache and precise interruption response was proposed. 15 of the MIPS instruction set were selected as the basic instruction for the CPU. By using 5 stage pipeline, the instruction Cache,data Cache and precise interruption response were realized. The teat results show that the scheme meets the design requirements.%提出了带Cache和精确中断响应的CPU设计方案,实现指令集MIPS中选取15条指令作为本CPU的基本指令.采用基本5步流水线CPU设计,给出了指令Cache、数据Cache和精确中断响应的设计与实现.测试结果表明,该方案符合设计要求.
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