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Parallel point-multiplication architecture using combined group operations for high-speed cryptographic applications

机译:使用组合组运算的并行点乘法架构用于高速密码应用

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摘要

In this paper, we propose a novel parallel architecture for fast hardware implementation of elliptic curve point multiplication (ECPM), which is the key operation of an elliptic curve cryptography processor. The point multiplication over binary fields is synthesized on both FPGA and ASIC technology by designing fast elliptic curve group operations in Jacobian projective coordinates. A novel combined point doubling and point addition (PDPA) architecture is proposed for group operations to achieve high speed and low hardware requirements for ECPM. It has been implemented over the binary field which is recommended by the National Institute of Standards and Technology (NIST). The proposed ECPM supports two Koblitz and random curves for the key sizes 233 and 163 bits. For group operations, a finite-field arithmetic operation, e.g. multiplication, is designed on a polynomial basis. The delay of a 233-bit point multiplication is only 3.05 and 3.56 μs, in a Xilinx Virtex-7 FPGA, for Koblitz and random curves, respectively, and 0.81 μs in an ASIC 65-nm technology, which are the fastest hardware implementation results reported in the literature to date. In addition, a 163-bit point multiplication is also implemented in FPGA and ASIC for fair comparison which takes around 0.33 and 0.46 μs, respectively. The area-time product of the proposed point multiplication is very low compared to similar designs. The performance (1Area×Time=1AT) and Area × Time × Energy (ATE) product of the proposed design are far better than the most significant studies found in the literature.
机译:在本文中,我们提出了一种新颖的并行架构,用于椭圆曲线点乘法(ECPM)的快速硬件实现,这是椭圆曲线密码处理器的关键操作。通过在雅可比投影坐标系中设计快速椭圆曲线组运算,可以在FPGA和ASIC技术上综合二进制字段上的点乘法。提出了一种新颖的组合点加倍和加点(PDPA)体系结构用于组操作,以实现ECPM的高速和低硬件要求。它已在美国国家标准技术研究院(NIST)推荐的二进制字段中实现。提议的ECPM支持两种Koblitz和随机曲线,密钥大小分别为233位和163位。对于分组运算,使用有限域算术运算,例如乘法是在多项式的基础上设计的。在Xilinx Virtex-7 FPGA中,分别用于Koblitz和随机曲线的233位点乘法的延迟分别仅为3.05和3.56μs,而在ASIC 65-nm技术中,则为0.81μs,这是最快的硬件实现结果迄今为止在文献中已有报道。此外,为了公平比较,在FPGA和ASIC中还实现了163位点乘法,分别耗时约0.33和0.46μs。与类似的设计相比,建议的点乘法的时空积非常低。性能(<数学xmlns:mml =“ http://www.w3.org/1998/Math/MathML” id =“ M1” overflow =“ scroll”> 1 A r e a × T i m e = 1 < / mn> A T )和面积×时间×能量(ATE)的乘积提出的设计远远优于文献中最重要的研究。

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