A CMOS ASIC Design for SiPM Arrays

机译：一个CmOs asIC设计的sipm阵列

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Our lab has previously reported on novel board-level readout electronics for an 8×8 silicon photomultiplier (SiPM) array featuring row/column summation technique to reduce the hardware requirements for signal processing. We are taking the next step by implementing a monolithic CMOS chip which is based on the row-column architecture. In addition, this paper explores the option of using diagonal summation as well as calibration to compensate for temperature and process variations. Further description of a timing pickoff signal which aligns all of the positioning (spatial channels) pulses in the array is described. The ASIC design is targeted to be scalable with the detector size and flexible to accommodate detectors from different vendors. This paper focuses on circuit implementation issues associated with the design of the ASIC to interface our Phase II MiCES FPGA board with a SiPM array. Moreover, a discussion is provided for strategies to eventually integrate all the analog and mixed-signal electronics with the SiPM, on either a single-silicon substrate or multi-chip module (MCM).

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Samrat Dey; Lushon Banks; Shaw-Pin Chen; Wenbin Xu; Thomas K. Lewellen; Robert S. Miyaoka; Jacques C. Rudell;
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年(卷),期 -1(2011),-1
年度 -1
页码 732–737
总页数 20
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1. Performance Study of a Wide-Area SiPM Array, ASICs Controlled [J] . Gonzalez A.J., Majewski S., Barbera J., Nuclear Science, IEEE Transactions on . 2015,第1期

机译：ASIC控制的广域SiPM阵列的性能研究
2. Results of a combined monolithic crystal and an array of ASICs controlled SiPMs [J] . P. Conde, A.J. Gonzalez, L. Hernandez, Nuclear Instruments & Methods in Physics Research. Section A, Accelerators, Spectrometers, Detectors and Associated Equipment . 2014,第janaptaB期

机译：组合单片晶体和ASIC控制的SiPM阵列的结果
3. A 4 × 14-Gbps/ch VCSEL array driving ASIC in 65nm CMOS for high-energy physics experiments [J] . D. Guo, Q. Sun, D. Gong, Journal of instrumentation: an IOP and SISSA journal . 2019,第5期

机译：一个4×14-GBPS / CH VCSEL阵列驱动ASIC，在65nm CMOS中进行高能物理实验
4. A CMOS ASIC design for SiPM arrays [C] . Dey, Samrat, Banks, Lushon, Chen, Shaw-Pin, Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC), 2011 IEEE . 2011

机译：用于SiPM阵列的CMOS ASIC设计
5. Design and implementation of advanced encryption standard in FPGA and 0.18 micron CMOS-based ASIC. [D] . Liu, Lan. 2003

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6. A CMOS Front-End Interface ASIC for SiPM-based Positron Emission Tomography Imaging Systems [O] . Samrat Dey, Jacques C. Rudell, Thomas K. Lewellen, -1

机译：用于基于SiPM的正电子发射断层成像系统的CMOS前端接口ASIC
7. Results of a combined monolithic crystal and an array of ASICs controlled SiPMs [O] . P. Conde, A.J. González, L. Hernández, 2014

机译：合并单片晶体的结果和ASICS控制的SIPMS阵列
8. Bulk CMOS VLSI Technology Studies. Part 1. Scalable CMOS Design Rules. Part 2. CMOS Approaches to PLA (Programmable Logic Array) Design [R] . Trotter, J. D., Naini, A. K. R. 1985

机译：批量CmOs VLsI技术研究。第1部分：可扩展CmOs设计规则。第2部分pLa（可编程逻辑阵列）设计的CmOs方法

A CMOS ASIC Design for SiPM Arrays

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