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A Highly Reliable 5.8 GHz DSRC Wake-Up Receiver with an Intelligent Digital Controller for an ETC System

机译:具有高度可靠的5.8 GHz DSRC唤醒接收器具有智能数字控制器适用于ETC系统

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摘要

In this article, a highly reliable radio frequency (RF) wake-up receiver (WuRx) is presented for electronic toll collection (ETC) applications. An intelligent digital controller (IDC) is proposed as the final stage for improving WuRx reliability and replacing complex analog blocks. With IDC, high reliability and accuracy are achieved by sensing and ensuring the successive, configurable number of wake-up signal cycles before enabling power-hungry RF transceiver. The IDC and range communication (RC) oscillator current consumption is reduced by a presented self-hibernation technique during the non-wake-up period. For accommodating wake-up signal frequency variation and enhancing WuRx accuracy, a digital hysteresis is incorporated. To avoid uncertain conditions during poor and false wake-up, a watch-dog timer for IDC self-recovery is integrated. During wake-up, the digital controller consumes 34.62 nW power and draws 38.47 nA current from a 0.9 V supply. In self-hibernation mode, its current reduces to 9.7 nA. It is fully synthesizable and needs 809 gates for its implementation in a 130 nm CMOS process with a 94 × 82 µm area. The WuRx measured power consumption is 2.48 µW, has −46 dBm sensitivity, and a 0.484 mm² chip area.
机译:在本文中,为电子收费(ETC)应用提供了一种高度可靠的射频(RF)唤醒接收器(WURX)。建议智能数字控制器(IDC)作为改善Wurx可靠性和更换复杂模拟块的最终阶段。通过IDC,通过感测和确保掌握幂射频收发器之前的连续,可配置的唤醒信号周期来实现高可靠性和精度。在非唤醒期间,IDC和范围通信(RC)振荡器电流消耗减少了呈现的自冬眠技术。为了容纳唤醒信号频率变化并提高Wurx精度,并入数字滞后。为了避免在较差和错误唤醒期间的不确定条件,IDC自我恢复的观察犬计时器是集成的。在唤醒期间,数字控制器消耗34.62个NW功率,并从0.9 V电源绘制38.47 NA电流。在自冬眠模式下,其电流降低至9.7 na。它是完全合成的,需要809个门,以130nm CMOS处理中的实现,具有94×82μm区域。 WURX测量功耗为2.48μW,具有-46 dBm灵敏度和0.484mm²的芯片区域。

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