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An Ultra-Low-Power Embedded Processor with Variable Micro-Architecture

机译：具有可变微型架构的超低功耗嵌入式处理器

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Embedded processors are widely used in various systems working on different tasks with different workloads. A more complex micro-architecture leads to better peak performance and worse power consumption. Shutting down the units designed for performance enhancement could improve energy efficiency in low-workload scenarios. In this paper, we evaluated the energy distribution in various embedded processors. According to the analysis, pipeline registers and the dynamic branch predictor, which are employed for better peak performance, have great impacts on energy efficiency. Thus, we proposed an ultra-low-power processor with variable micro-architecture. The processor is based on a 4-stage pipeline core with a Gshare branch predictor, and all units work in high-performance mode. In normal mode, the Gshare predictor is shut down and Always-Not-Taken prediction is used. In low-power mode, some of the pipeline registers are bypassed to avoid unnecessary energy dissipation and improve executing efficiency. A mode register (MR) is designed to indicate current working mode. Switching between different modes is controlled by the software. The proposed core is implemented in 40 nm technology and simulated with the traces of 17 benchmarks in Embench. The average amounts of power consumed by the respective modes are 41.7 μW, 59.7 μW and 71.1 μW. The results show that normal mode (N-mode) and low-power mode (L-mode) consume 16.08% and 41.37% less power than high-performance mode (H-mode) on average. In best case scenarios, they could save 25.36% and 49.30% more power than H-mode. Considering the execution efficiency evaluated by instructions per cycle (IPC), the proposed processor consumes 7.78% or 51.57% less energy for each instruction than the baseline core. The area of the proposed processor is only 7.19% larger than the baseline core, and only 3.08% more power is consumed in H-mode.
机译：嵌入式处理器广泛用于各种系统，用于使用不同的工作负载的不同任务。更复杂的微架构导致更好的峰值性能和更糟糕的功耗。关闭设计用于性能增强的单位可以提高低工作量方案中的能效。在本文中，我们评估了各种嵌入式处理器中的能量分布。根据分析，管道寄存器和动态分支预测因子，用于更好的峰值性能，对能效产生很大影响。因此，我们提出了一种具有可变微架构的超低功耗处理器。处理器基于具有GShare分支预测器的4级管道核心，并且所有单元都以高性能模式工作。在正常模式中，GSHARE预测器被关闭，并且始终不采用预测。在低功耗模式下，绕过一些管道寄存器以避免不必要的能量耗散并提高执行效率。模式寄存器（MR）旨在指示当前的工作模式。在不同模式之间切换由软件控制。所提出的核心以40 nm的技术实施，并在EMBONH中使用17个基准的迹象进行模拟。各种模式消耗的平均功率量为41.7μW，59.7μW和71.1μW。结果表明，平均水平的正常模式（N模式）和低功耗模式（L-MODE）比高性能模式（H-MODE）的功率低16.08％和41.37％。在最佳案例方案中，它们可以节省25.36％和49.30％的功率高于H模式。考虑到每个周期（IPC）的指令评估的执行效率，所提出的处理器为每个指令消耗比基线核心的每个指令减少7.78％或51.57％。所提出的处理器的面积比基线核心大7.19％，在H模式下仅消耗了3.08％的功率。

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