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Particle MCMC algorithms and architectures for accelerating inference in state-space models

机译:用于加速状态空间模型中推理的粒子MCMC算法和体系结构

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摘要

Particle Markov Chain Monte Carlo (pMCMC) is a stochastic algorithm designed to generate samples from a probability distribution, when the density of the distribution does not admit a closed form expression. pMCMC is most commonly used to sample from the Bayesian posterior distribution in State-Space Models (SSMs), a class of probabilistic models used in numerous scientific applications. Nevertheless, this task is prohibitive when dealing with complex SSMs with massive data, due to the high computational cost of pMCMC and its poor performance when the posterior exhibits multi-modality. This paper aims to address both issues by: 1) Proposing a novel pMCMC algorithm (denoted ppMCMC), which uses multiple Markov chains (instead of the one used by pMCMC) to improve sampling efficiency for multi-modal posteriors, 2) Introducing custom, parallel hardware architectures, which are tailored for pMCMC and ppMCMC. The architectures are implemented on Field Programmable Gate Arrays (FPGAs), a type of hardware accelerator with massive parallelization capabilities. The new algorithm and the two FPGA architectures are evaluated using a large-scale case study from genetics. Results indicate that ppMCMC achieves 1.96x higher sampling efficiency than pMCMC when using sequential CPU implementations. The FPGA architecture of pMCMC is 12.1x and 10.1x faster than state-of-the-art, parallel CPU and GPU implementations of pMCMC and up to 53x more energy efficient; the FPGA architecture of ppMCMC increases these speedups to 34.9x and 41.8x respectively and is 173x more power efficient, bringing previously intractable SSM-based data analyses within reach.
机译:粒子马尔可夫链蒙特卡罗(pMCMC)是一种随机算法,设计用于在概率密度分布不​​允许封闭形式表达式时从概率分布生成样本。 pMCMC最常用于从状态空间模型(SSM)中的贝叶斯后验分布中采样,状态空间模型(SSM)是一种在许多科学应用中使用的概率模型。然而,由于pMCMC的计算成本高,并且后验显示多模态时性能较差,因此在处理具有大量数据的复杂SSM时,此任务是禁止的。本文旨在通过以下两种方法解决这两个问题:1)提出一种新颖的pMCMC算法(称为ppMCMC),该算法使用多个马尔可夫链(而不是pMCMC所使用的链)来提高多模式后验的采样效率; 2)引入自定义方法,为pMCMC和ppMCMC量身定制的并行硬件架构。这些架构是在现场可编程门阵列(FPGA)上实现的,FPGA是一种具有大量并行化功能的硬件加速器。这项新算法和这两种FPGA体系结构是通过遗传学的大规模案例研究进行评估的。结果表明,使用顺序CPU实现时,ppMCMC的采样效率是pMCMC的1.96倍。 pMCMC的FPGA体系结构比最新的pMCMC并行CPU和GPU实现快12.1倍和10.1倍,并且能效高出53倍。 ppMCMC的FPGA体系结构将这些速度分别提高了34.9倍和41.8倍,并且电源效率提高了173倍,从而使以前难以处理的基于SSM的数据分析成为可能。

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