• 主题
高级搜索  >
历史搜索 清空历史
首页> 外文期刊>ACM Computing Surveys >Methods for Fault Tolerance in Networks-on-Chip
【24h】

Methods for Fault Tolerance in Networks-on-Chip

机译：片上网络中的容错方法

获取原文
获取原文并翻译 | 示例
           
页面导航
  • 摘要
  • 著录项
  • 相似文献
  • 相关主题

摘要

Networks-on-Chip constitute the interconnection architecture of future, massively parallel multiprocessors that assemble hundreds to thousands of processing cores on a single chip. Their integration is enabled by ongoing miniaturization of chip manufacturing technologies following Moore's Law. It comes with the downside of the circuit elements' increased susceptibility to failure. Research on fault-tolerant Networks-on-Chip tries to mitigate partial failure and its effect on network performance and reliability by exploiting various forms of redundancy at the suitable network layers. The article at hand reviews the failure mechanisms, fault models, diagnosis techniques, and fault-tolerance methods in on-chip networks, and surveys and summarizes the research of the last ten years. It is structured along three communication layers: the data link, the network, and the transport layers. The most important results are summarized and open research problems and challenges are highlighted to guide future research on this topic.
机译：片上网络构成了未来的大规模并行多处理器的互连架构，这些处理器在单个芯片上组装了数百至数千个处理内核。遵循摩尔定律，芯片制造技术的不断小型化实现了它们的集成。随之而来的是电路元件增加了对故障的敏感性。容错片上网络的研究试图通过在适当的网络层利用各种形式的冗余来减轻部分故障及其对网络性能和可靠性的影响。这篇文章回顾了片上网络的故障机理，故障模型，诊断技术和容错方法，并对最近十年的研究进行了总结和总结。它由三个通信层构成：数据链路，网络和传输层。总结了最重要的结果，并突出了开放的研究问题和挑战，以指导有关该主题的未来研究。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱：kefu@zhangqiaokeyan.com

京公网安备：11010802029741号 ICP备案号：京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有

  • 客服微信

  • 服务号