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A fault-tolerant approach to test control utilizing dual-redundant processors

机译:使用双冗余处理器的容错测试控制方法

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摘要

A simple dual-redundant fault-tolerant test control system architecture has been designed, developed, and demonstrated in a real-time environment using inexpensive persona! computers. A survey of existing fault-tolerant control systems was performed to assess the relative cost and capabilities of currently available technology. A cost-benefit analysis was performed comparing the relative benefit of this system to triplex systems and non-fault-tolerant systems for various applications. Functionally identical implementations of a prototype proof-of-concept software design were constructed in two different languages and tested using a unit-under-test model. Bugs (faults) were injected into this model to verify the ability of the system to reliably detect anomalous test hardware operation. Also, simulated bugs (faults) were introduced to verify smooth control transfer between primary and standby, both nominally and in the presence of hard-ware-under-tests anomalies. Results indicate significant improvement in system reliability, sufficient to justify the additional cost of the proposed duplex system for many potential users.
机译:已经设计,开发了简单的双冗余容错测试控制系统体系结构,并使用廉价角色在实时环境中进行了演示!电脑。对现有的容错控制系统进行了调查,以评估当前可用技术的相对成本和功能。进行了成本效益分析,比较了该系统与三重系统和非容错系统在各种应用中的相对优势。用两种不同的语言构造了原型概念验证软件设计的功能相同的实现,并使用了被测单元模型进行了测试。将错误(错误)注入此模型以验证系统可靠地检测异常测试硬件操作的能力。此外,还引入了模拟错误(故障)以验证名义上和存在被测硬件异常情况下主备数据库之间的平滑控制转换。结果表明,系统可靠性有了显着提高,足以为许多潜在用户证明所提议的双工系统的额外成本。

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