VLSI architecture for SAR data compression

Jeong H.; Park J.H.; Ryu H.Y.; Kwon J.B.; Oh Y.

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VLSI architecture for SAR data compression

机译：SAR数据压缩的VLSI架构

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As a step towards a real-time signal aperture radar (SAR) correlator, custom very large scale integration (VLSI) architectures are developed. Considering the extremely short word length of the data, we derive three architectures with massive parallelism in bit space. Unlike frequency methods, no. degradation is introduced during convolution. Optimized for time and space, they are highly suited to VLSI implementation, and a small architecture with 80 taps operating at 10 MHz has been built using an FPGA

机译：作为迈向实时信号孔径雷达（SAR）相关器的一步，开发了定制的超大规模集成（VLSI）体系结构。考虑到数据的字长非常短，我们得出了在位空间中具有大规模并行性的三种架构。与频率方法不同，没有。在卷积期间引入了退化。针对时间和空间进行了优化，它们非常适合VLSI实施，并且已经使用FPGA构建了一个小型架构，该架构具有以10 MHz运行的80个抽头

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《IEEE Transactions on Aerospace and Electronic Systems》 |2002年第2期|p.427-440|共14页
作者
Jeong H.; Park J.H.; Ryu H.Y.; Kwon J.B.; Oh Y.;
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正文语种 eng
中图分类航空;
关键词
VLSI; adders; application specific integrated circuits; computational complexity; convolution; correlators; data compression; field programmable gate arrays; image coding; image processing equipment; parallel architectures; pipeline processing; radar computing; radar;

机译：VLSI;加法器;专用集成电路;计算复杂度;卷积;相关器;数据压缩;现场可编程门阵列;图像编码;图像处理设备;并行体系结构;管道处理;雷达计算;雷达;

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VLSI architecture for SAR data compression

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