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首页> 外文期刊>IEEE Transactions on Aerospace and Electronic Systems >A hardware-efficient, multirate, digital channelized receiverarchitecture
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A hardware-efficient, multirate, digital channelized receiverarchitecture

机译：硬件高效，多速率，数字通道化接收器架构

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摘要

An approach is presented to realizing a digital channelized receiver for signal intercept applications that provides a hardware efficient implementation of a uniform filter bank in which the number of filters K is greater than the decimation factor M. The proposed architecture allows simple channel arbitration logic to be used and provides reliable instantaneous frequency measurements, even in adjacent channel crossover regions. In the proposed implementation of the filter bank, K is related to M by K=FM where F is an integer. It is shown that the optimum selection of F allows the instantaneous frequency measurement to be made in the channel crossover region and the arbitration function to be based solely on the instantaneous frequency measurement. The development of a filter bank structure which combines the flexibility of the short-time Fourier transform (STFT) with the implementation efficiency of the polyphase filter bank decomposition, meeting these requirements and leading to a hardware-efficient implementation, is presented
机译：提出了一种用于信号截取应用的数字信道化接收器的实现方法，该方法提供了统一的滤波器组的硬件有效实现，其中滤波器的数量K大于抽取因子M。所提出的体系结构允许简单的信道仲裁逻辑成为即使在相邻的信道交叉区域中，它也能提供可靠的瞬时频率测量。在所提出的滤波器组的实现中，K与M的关系为K = FM，其中F为整数。结果表明，F的最佳选择允许在信道交叉区域中进行瞬时频率测量，而仲裁函数仅基于瞬时频率测量。提出了一种将短时傅立叶变换（STFT）的灵活性与多相滤波器组分解的实现效率相结合的滤波器组结构的开发，以满足这些要求并实现了硬件高效的实现

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