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首页> 外文期刊>Applied Computational Electromagnetics Society journal >FPGA Based Fast Bartlett DoA Estimator for ULA Antenna Using Parallel Computing
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FPGA Based Fast Bartlett DoA Estimator for ULA Antenna Using Parallel Computing

机译：基于FPGA的ULA天线快速Bartlett DoA估计器的并行计算。

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摘要

This paper presents a design and implementation of a structure which uses Bartlett Direction of Arrival (DoA) algorithm and a receiver system on Altera Cyclone IV and Cyclone III FPGAs. First of all, a software defined radio (SDR) that has 4 simultaneous inputs, is designed. All data used in this study are obtained by using this radio system. Then one of the FPGA is configured as antenna simulator and the other one is used for implementing Bartlett DoA estimation algorithm. Bartlett DoA estimation algorithm is developed completely in parallel and compared with a previous study which is performed sequentially on an FPGA using NIOS processor. The designs are tested by using 4-element Uniform Linear Array (ULA) antenna. Implemented hardware is compared in terms of DoA calculation speed and the sources that occupy on the FPGA. Furthermore, the paper has significant improvement in calculation duration thereby achieving lower response latency compared with previously published similar works.
机译：本文介绍了一种使用Bartlett到达方向（DoA）算法和Altera Cyclone IV和Cyclone III FPGA上的接收器系统的结构的设计和实现。首先，设计了具有4个同时输入的软件定义无线电（SDR）。本研究中使用的所有数据均通过使用该无线电系统获得。然后将其中一个FPGA配置为天线模拟器，另一个用于实现Bartlett DoA估计算法。 Bartlett DoA估计算法是完全并行开发的，并且与先前的研究相比较，后者是使用NIOS处理器在FPGA上顺序执行的。通过使用4元素均匀线性阵列（ULA）天线对设计进行测试。比较已实现的硬件的DoA计算速度和FPGA上的资源。此外，与以前发表的类似作品相比，该论文在计算持续时间上有显着改善，从而实现了更低的响应延迟。

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