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首页> 外文期刊>Applied Physics >Integration of ferroelectric BIT and dielectric HfO_2 on silicon substrate with high data retention and endurance for ferroelectric FET applications
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Integration of ferroelectric BIT and dielectric HfO_2 on silicon substrate with high data retention and endurance for ferroelectric FET applications

机译：在硅衬底上集成铁电BIT和电介质HfO_2，具有高数据保留能力和耐久性，适用于铁电FET应用

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摘要

For this proposed work, the electrical and ferroelectric properties of metal-ferroelectric-insulator-silicon (MFeIS) and metal-ferroelectric-insulator-metal (MFeIM) capacitors with Bi4Ti3O12 (BIT) ferroelectric film deposited on HfO2/Si substrate were investigated. Physical vapor deposition technique (RF sputtering) was carried out for the deposition of 100 nm ferroelectric and high-k dielectric film of 5, 10 and 15 nm thickness. The structural properties such as crystallographic phase, grain size with composition and refractive index of the deposited films were measured by X-ray diffraction, field emission scanning electron microscopy with energy dispersive spectroscopy (FESEM-EDS) and multiple angle ellipsometry. Metal/ferroelectric/silicon (MFeS), metal/ferroelectric/metal (MFeM), metal/insulator/silicon (MIS), MFeIS and MFeIM structures were fabricated to obtain the electrical and ferroelectric properties. Investigation shows that the MFeIS structure with 10 nm buffer layer demonstrates improved memory window of 8.81 V as compared to the 3.3 V in the MFeS structure. MFeIM with 10 nm HfO2 buffer layer shows maximum remnant polarization of 4.05 mu C/cm(2). MFeI (10 nm) S structure even shows endurance higher than 10(13) read/write cycles and data retention for more than 10 years. The reliability of the ferroelectric and ferroelectric/dielectric stack was obtained by measuring the breakdown voltage characteristics.
机译：对于这项拟议的工作，研究了在HfO2 / Si衬底上沉积有Bi4Ti3O12（BIT）铁电薄膜的金属-铁电绝缘体-硅（MFeIS）和金属-铁电绝缘体-金属（MFeIM）电容器的电和铁电性能。进行物理气相沉积技术（RF溅射）以沉积厚度为5、10和15 nm的100 nm铁电和高k电介质膜。通过X射线衍射，具有能量色散谱的场发射扫描电子显微镜（FESEM-EDS）和多角度椭圆光度法来测量诸如沉积相的结晶相，晶粒尺寸，组成和折射率的结构性质。制造金属/铁电/硅（MFeS），金属/铁电/金属（MFeM），金属/绝缘体/硅（MIS），MFeIS和MFeIM结构以获得电和铁电性能。研究表明，与MFeS结构中的3.3 V相比，具有10 nm缓冲层的MFeIS结构的存储窗口提高了8.81V。具有10 nm HfO2缓冲层的MFeIM显示最大残留极化为4.05μC / cm（2）。 MFeI（10 nm）S结构甚至显示出超过10（13）个读/写周期的耐久性，并且数据保留超过10年。通过测量击穿电压特性获得铁电体和铁电体/电介质叠层的可靠性。

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  • 来源
    《Applied Physics》 |2019年第11期|798.1-798.12|共12页
  • 作者

    Jha Rajesh Kumar; Singh Prashant; Goswami Manish; Singh B. R.;

  • 作者单位

    Indian Inst Informat Technol Dept Elect & Commun Engn Allahabad 211015 Uttar Pradesh India;

  • 收录信息 美国《科学引文索引》(SCI);美国《工程索引》(EI);美国《生物学医学文摘》(MEDLINE);
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