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首页> 外文期刊>Applied Surface Science >Influence Of Si/sio_2 Interface Properties On Electrical Performance And Breakdown Characteristics Of Ultrathin Stacked Oxideitride Dielectric Films
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Influence Of Si/sio_2 Interface Properties On Electrical Performance And Breakdown Characteristics Of Ultrathin Stacked Oxideitride Dielectric Films

机译：Si / sio_2界面性质对超薄氧化物/氮化物介质薄膜电性能和击穿特性的影响

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摘要

In this work, the influence of Si/SiO_2 interface properties, interface nitridation and remote-plasma-assisted oxidation (RPAO) thickness (< 1 nm), on electrical performance and TDDB characteristics of sub-2 nm stacked oxideitride gate dielectrics has been investigated using a constant voltage stress (CVS). It is demonstrated that interfacial plasma nitridation improves the breakdown and electrical characteristics. In the case of PMOSFETs stressed in accumulation, interface nitridation suppresses the hole traps at the Si/SiO_2 interface evidenced by less negative V_t shifts. Interface nitridation also retards hole tunneling between the gate and drain, resulting in reduced off-state drain leakage. In addition, the RPAO thickness of stacked gate dielectrics shows a profound effect in device performance and TDDB reliability. Also, it is demonstrated that TDDB characteristics are improved for both PMOS and NMOS devices with the 0.6 nm-RPAO layer using Weibull analysis. The maximum operating voltage is projected to be improved by 0.3 V difference for a 10-year lifetime. However, physical breakdown mechanism and effective defect radius during stress appear to be independent of RPAO thickness from the observation of the Weibull slopes. A correlation between trap generation and dielectric thickness changes based on the C-V distortion and oxide thinning model is presented to clarify the trapping behavior in the RPAO and bulk nitride layer during CVS stress.
机译：在这项工作中，Si / SiO_2界面特性，界面氮化和远程等离子体辅助氧化（RPAO）厚度（<1 nm）对亚2 nm堆叠氧化物/氮化物栅电介质的电性能和TDDB特性的影响使用恒定电压应力（CVS）进行了研究。结果表明，界面等离子体氮化改善了击穿性能和电学特性。在PMOSFET累积应力过大的情况下，界面氮化可抑制Si / SiO_2界面处的空穴陷阱，而负V_t漂移较小。界面氮化还阻碍了栅极和漏极之间的空穴隧穿，从而减少了截止状态漏极的泄漏。此外，堆叠栅极电介质的RPAO厚度对器件性能和TDDB可靠性显示出深远的影响。此外，使用威布尔分析证明，对于具有0.6 nm-RPAO层的PMOS和NMOS器件，TDDB特性均得到改善。预计最大工作电压将在10年的使用寿命内提高0.3 V的差异。然而，从威布尔斜率的观察来看，物理破坏机理和应力作用下的有效缺陷半径似乎与RPAO厚度无关。提出了基于C-V畸变和氧化物稀化模型的陷阱产生与电介质厚度变化之间的相关性，以阐明CVS应力期间RPAO和体氮化物层中的陷阱行为。

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