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首页> 外文期刊>Arabian Journal for Science and Engineering. Section A, Sciences >Design of Efficient Ternary Operators for Scrambling in CNTFET Technology
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Design of Efficient Ternary Operators for Scrambling in CNTFET Technology

机译：CNTFET技术中争夺高效三元运营商的设计

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摘要

Digital computation using ternary logic allows compact and energy-efficient digital design due to the reduction in circuit interconnects and chip area. CNFET unique characteristic of scalable threshold voltage value by utilizing the CNTs of different chirality vectors makes it a suitable option to realize ternary logic designs. This work presents hardware-efficient and low-power ternary operators exclusively used for scrambling applications in crypto-algorithms. The proffered designs are based on multiplexing the output digits among various unary cycle operators as the input trits. Extensive HSPICE simulations are conducted using standard 32-nm CNFET Stanford model to calculate the performance parameters of the proposed circuits. The presented designs show a significant improvement in terms of average power consumption, component count and energy consumption as compared to earlier counterparts. Results for various proposed scrambling operators Sop3, Sop4 and Sop5 show about an average reduction in energy consumption of 80% as compared to previously presented scrambling operators. Moreover, the Monte Carlo simulation results reveal that the proposed designs are robust against the mismatches in the diameter of CNTs.
机译：由于电路互连和芯片区域的减少，使用三元逻辑的数字计算允许紧凑且节能的数字设计。 CNFET通过利用不同性行道向量的CNT来实现可扩展阈值电压值的独特特性使其成为实现三元逻辑设计的合适选择。这项工作提供了硬件高效和低功耗的三元运算符，专门用于加密算法中的扰扰应用。提供的设计基于将各种联合循环运算符之间的输出数字复用为输入速度。使用标准的32-NM CNFET斯坦福模型进行广泛的HSPICE模拟，以计算所提出的电路的性能参数。与早期对应相比，所呈现的设计表现出平均功耗，组件计数和能耗的显着改进。与先前呈现的扰扰器相比，各种提出的加扰算子SOP3，SOP4和SOP5的平均降低了80％的平均降低。此外，蒙特卡罗模拟结果表明，所提出的设计对CNT直径的不匹配是鲁棒的。

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