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首页> 外文期刊>Arabian Journal for Science and Engineering. Section A, Sciences >Logically Optimal Novel 4:2 Compressor Architectures for High-Performance Applications
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Logically Optimal Novel 4:2 Compressor Architectures for High-Performance Applications

机译：逻辑上最佳的新颖4：2用于高性能应用的压缩机架构

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摘要

Multipliers are principal arithmetic components that play a key role in determining the performance of DSP architectures. While the efficiency of multipliers relies on optimal reduction of partial products within constraint power-delay values, this can be achieved by ‘compressors' a precisely designed special arithmetic module. In this manuscript, authors propose low-power high-performance 4:2 compressor architectures. The presented designs perform better than the contemporary designs in terms of latency, improved power-delay and area-delay product values. The principal objective of this work is to design and develop a fast 4:2 compressor circuitry with optimal trade-off between power and area by pristine logical decomposition. All the referenced and proposed designs are simulated and synthesized in synopsys design compiler using prelayout CMOS standard cell library ofTSMC65 nm. From the synthesis results, it can be seen that the proposed model provides 12.5–29.17% reduction in area and 7–14.23% reduction in propagation delay with respect to state-of-the-art 4:2 compressor designs. In addition, to estimate the performance stability in realistic applications, 4-bit, 8-bit and 16-bit Dadda multiplier integrated with proposed compressor cells is implemented and verified. The obtained synthesis results substantiate that Dadda multiplier integrated with proposed compressor cells performs better than conventional and state-of-the-art 4:2 compressor-based variants with 4–8% reduction in propagation delay, upto 23.370% reduction in area-delay product and upto 25.62% reduction in power-delay product for 4-bit multiplication, while 6.77–16.85% reduction in propagation delay, 2.62–18.70% reduction in area-delay product and 15.30–23.20% reduction in power-delay product are achieved for 8-bit multiplication. For 16-bit multiplication it shows upto 47.05% reduction in propagation delay, upto 21.68% reduction in area-delay product and upto 24.42% reduction in power-delay product for 16-bit multiplication.
机译：乘数是主要算术组件，可在确定DSP架构的性能方面发挥关键作用。虽然乘数的效率依赖于约束电源延迟值内的部分产品的最佳减少，但这可以通过“压缩机”精确设计的特殊算术模块来实现。在本手稿中，作者提出了低功耗的高性能4：2压缩机架构。本设计的设计比在延迟，改进的电源延迟和面积延迟产品值方面的表现优于当代设计。这项工作的主要目标是设计和开发快速的4：2压缩机电路，通过原始逻辑分解，功率和面积之间的最佳折衷。所有引用的和提出的设计都是在Synopsys设计编译器中模拟和合成，使用PRERAYOUT CMOS标准单元库库，Synopsys Design Comber库库。从合成结果中，可以看出，所提出的模型降低了12.5-29.17％的面积，并且传播延迟减少了7-14.23％，相对于最先进的4：2压缩机设计。另外，为了估计现实应用中的性能稳定性，实现并验证了与所提出的压缩机单元集成的4位，8位和16位DADDA乘法器。所获得的合成结果证实了与所提出的压缩机电池集成的Dadda倍增器比传统和最先进的4：2的基于压缩机的变体更好，传播延迟减少4-8％，面积延迟减少了23.370％产品和高达25.62％的功率延迟产品减少4位倍增，而传播延迟的减少6.77-16.85％，面积延迟产品的减少2.62-18.70％，达到动力延迟产品的15.30-23.20％对于8位乘法。对于16位倍增，它的传播延迟降低了47.05％，面积延迟产品的减少高达21.68％，功率延迟产品的减少高达24.42％，用于16位乘法。

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