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A degradable NoC router for the improvement of fault-tolerant routing performance

机译：用于改善容错路由性能的可降解NOC路由器

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摘要

Network-on-chip (NoC) provides high computation performance for a wide range of applications including robotics and artificial intelligence. This paper deals with the issue of improving the fault-tolerant routing performance for realizing high-performance NoCs. The major drawbacks of the conventional fault-tolerant routing methods are low node utilization efficacy and high communication latency. To solve these problems, we propose a novel NoC router which enables to logically reconstruct faulty input buffers. In contrast to most conventional methods, where routers with partially faulty input buffers are regarded as faulty, the proposed method regards them as fault-free routers with degraded input buffers. Simulation results obtained by a cycle accurate custom simulator show that the proposed method reduces the number of faulty and unused nodes and improves communication latency by up to 93% and 87%, respectively, compared with the conventional methods.
机译：片上网（NOC）为广泛的应用提供了高计算性能，包括机器人和人工智能。本文涉及提高容错路由性能的问题，以实现高性能NOCS。传统的容错路由方法的主要缺点是低节点利用功效和高通信等待时间。为了解决这些问题，我们提出了一种新的NoC路由器，它可以逻辑重建故障的输入缓冲区。与大多数传统方法相比，其中具有部分故障输入缓冲区的路由器被视为错误，所提出的方法将它们视为具有劣化的输入缓冲区的无故障路由器。通过循环准确的定制模拟器获得的仿真结果表明，该方法还减少了故障和未使用的节点的数量，与传统方法相比，分别将通信延迟提高至多93％和87％。

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