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首页> 外文期刊>Canadian journal of electrical and computer engineering >Automatic and Simultaneous Floorplanning and Placement in Field-Programmable Gate Arrays With Dynamic Partial Reconfiguration Based on Genetic Algorithm
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Automatic and Simultaneous Floorplanning and Placement in Field-Programmable Gate Arrays With Dynamic Partial Reconfiguration Based on Genetic Algorithm

机译：基于遗传算法的动态部分重新配置，在现场可编程门阵列中自动和同步平面图和放置

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摘要

Using dynamic partial reconfiguration (DPR) feature in field-programmable gate array (FPGA) systems seems inevitable by considering the tremendous benefits, such as reduced cost and power. Nowadays, manual floorplanning is one of the difficulties in implementing DPR systems, which relies on the designer's views and his command over designing the concepts for arranging the modules on the physical layout of the FPGA more efficiently, as the results of floorplanning can influence the next stages, such as the placement. In other words, placement and floorplanning that are separately conducted in the today's tools are interdependent and the floorplanning results play a role in the placement and vice versa. This article aimed to propose a method for conducting floorplanning and placement simultaneously in DPR systems according to the genetic algorithm (GA). The proposed algorithm was tested on 20 largest MCNC benchmark circuits with DPR-support capability. Based on the results, wirelength and critical path delay improved by 14% and 17%, respectively, compared with Xilinx's early access partial reconfiguration design flow (EAPR). However, area and runtime increased by about 2% and 8%, respectively. The proposed method was also compared with other research that uses B* tree and simulated annealing algorithm. The results showed that our proposed algorithm is competitive in various parameters with other research.
机译：在现场可编程门阵列（FPGA）系统中使用动态部分重新配置（DPR）功能似乎是不可避免的，考虑到巨大的益处，例如降低成本和功率。如今，手动平面图是实施DPR系统的困难之一，它依赖于设计师的观点和他的命令设计用于更有效地为FPGA的物理布局安排模块的概念，因为平面图的结果可以影响下一个阶段，如放置。换句话说，在今天的工具中单独进行的放置和平面图是相互依存的，地板平移结果在放置中发挥作用，反之亦然。本文旨在提出根据遗传算法（GA）在DPR系统中同时进行平面图和放置的方法。该算法在20大MCNC基准电路上测试了DPR - 支持能力。基于结果，与Xilinx早期访问部分重新配置流（EAPR）相比，WireLength和Critical Path延迟分别提高了14％和17％。然而，区域和运行时间分别增加了约2％和8％。该方法还与使用B *树和模拟退火算法的其他研究进行了比较。结果表明，我们所提出的算法与其他研究的各种参数具有竞争力。

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