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A Novel Design of Efficient Multi-channel UART Controller Based on FPGA

机译:基于FPGA的高效多通道UART控制器的新型设计

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摘要

In traditional universal asynchronous receiver transmitter (UART) controller, the data transmission is inefficient and the data bus utilization ratio is low. A novel design is provided to solve these problems. The architecture of the system is introduced, the flow charts of data processing as well as the implementation state machine are also presented in detail. This paper is concluded by comparing the performance of this design, which is realized on field programmable gate array (FPGA) using Verilog hardware description language (HDL), with other traditional UART controllers.
机译:在传统的通用异步收发器(UART)控制器中,数据传输效率低,数据总线利用率低。提供了新颖的设计来解决这些问题。介绍了系统的体系结构,详细介绍了数据处理的流程图以及实现状态机。本文通过比较该设计的性能得出结论,该设计是使用Verilog硬件描述语言(HDL)在现场可编程门阵列(FPGA)上与其他传统UART控制器实现的。

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