A Low-Power 8-GS/s Comparator for High-Speed Analog-to-Digital Conversion in <inline-formula> <tex-math notation='LaTeX'>$0.13mu$ </tex-math></inline-formula>m CMOS Technology

Mohtashemi Darya; Green Michael M.

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$0.13mu$

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A Low-Power 8-GS/s Comparator for High-Speed Analog-to-Digital Conversion in $0.13mu$ m CMOS Technology

机译：用于以 $ 0.13 mu $ inline-formula>的高速模数转换的低功耗8-GS / s比较器/ inline-formula> m CMOS技术

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This brief presents a novel comparator circuit design for high-speed analog-to-digital converters in data communication systems. The circuit achieves higher bandwidth compared to existing architectures, without the use of bandwidth enhancing inductors. Implemented in 0.13 mu m CMOS technology, the proposed comparator operates from a 1.2V supply and consumes a total power of 2.4mW, with sampling speeds up to 8-GS/s.

机译：本简介提出了一种新颖的比较器电路设计，用于数据通信系统中的高速模数转换器。与现有架构相比，该电路可实现更高的带宽，而无需使用带宽增强电感器。拟议的比较器采用0.13μmCMOS技术实现，采用1.2V电源供电，总功耗为2.4mW，采样速度高达8-GS / s。

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来源
《Circuits and Systems II: Express Briefs, IEEE Transactions on》 |2019年第4期|557-561|共5页
作者
Mohtashemi Darya; Green Michael M.;
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作者单位

Univ Calif Irvine, Irvine, CA 92697 USA|DNA Elect, London W12 7SB, England;

Univ Calif Irvine, Dept Elect Engn & Comp Sci, Irvine, CA 92697 USA;

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原文格式 PDF
正文语种 eng
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关键词
Analog-to-digital converters (ADCs); CMOS integrated circuits; high-speed comparators; low-power;

机译：模数转换器（ADC）;CMOS集成电路;高速比较器;低功率;

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1. A Low-Power 8-GS/s Comparator for High-Speed Analog-to-Digital Conversion in $0.13mu$ m CMOS Technology [J] . Mohtashemi Darya, Green Michael M. Circuits and Systems II: Express Briefs, IEEE Transactions on . 2019,第4期

机译：低功耗8-GS / S比较器，用于<内联公式> $ 0.13 MU $ M CMOS技术
2. Secure Satellite Communication Digital IF CMOS $Q$ -Band Transmitter and $K$ -Band Receiver [J] . LaRocca Tim R., Thai Khanh, Snyder Robert, IEEE Journal of Solid-State Circuits . 2019,第5期

机译：安全卫星通信数字IF CMOS $ Q $ -频段发送器和 $ K $ -频段接收器
3. Secure Satellite Communication Digital IF CMOS $Q$ -Band Transmitter and $K$ -Band Receiver [J] . LaRocca Tim R., Thai Khanh, Snyder Robert, IEEE Journal of Solid-State Circuits . 2019,第5期

机译：安全卫星通信数字如果cmos <内联公式> $ q $ -band发射器和 $ k $ $ -band接收器
4. Study of Performance of High-Speed Low-Power Differential Input Based Dynamic Comparator Using 22 nm CMOS Technology [C] . P.M. Aarthi, A. Dinesh, T. Janani, International Conference on Advanced Computing and Communication Systems . 2020

机译：基于22 nm CMOS技术的高速低功耗差分输入动态比较器性能研究
5. Low-power high-speed low-offset fully dynamic CMOS latched comparator [D] . Jeon, HeungJun. 2010

机译：低功耗高速低偏移完全动态CMOS锁存器
6. A Compact Resistor-Based CMOS Temperature Sensor With an Inaccuracy of 0.12 °C (3 $sigma$ ) and a Resolution FoM of 0.43 pJ $cdot$ K $^{2}$ in 65-nm CMOS [O] . Woojun Choi, Yongtae Lee, Seonhong Kim, 2018

机译：基于紧凑的电阻式CMOS温度传感器，其不准确为0.12°C（3 $ Sigma $ ）和0.43 pj $ cdot $ k $ ^ {2} $ 65-nm cmos

A Low-Power 8-GS/s Comparator for High-Speed Analog-to-Digital Conversion in $0.13mu$ m CMOS Technology

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