The design of an all-digital phase-locked loop with small DCOhardware and fast phase lock

Jen-Shiun Chiang; Kuang-Yuan Chen

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The design of an all-digital phase-locked loop with small DCOhardware and fast phase lock

机译：具有小型DCO硬件和快速锁相功能的全数字锁相环的设计

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The cores of the all-digital phase-locked loop (ADPLL) are thenswitch-tuning digital control oscillator (DCO) and the architecture, Innthis brief, we propose a DCO with reduced hardware cost, andnarchitecture with characteristics of fast frequency locking, fullndigitization, easy design and implementation, and good stability. It isnsuitable to be used as the clock generator for high-performancenmicroprocessors. The prototype of a 3.3-V ADPLL chip has been designednby TSMC's 0.6 Μm SPDM CMOS process. The simulation shows that thisnADPLL can operate in the range between 60 and 400 MHz, and at four timesnthe reference clock frequency. The phase-lock process takes 47 clockncycles, and the phase error is less than 0.1 ns

机译：然后，全数字锁相环（ADPLL）的核心是开关调谐数字控制振荡器（DCO）和该架构，Inn此简介，我们提出了一种具有降低的硬件成本的DCO，以及具有快速锁频，全数字化，设计和实现容易，稳定性好。它不适合用作高性能微处理器的时钟发生器。台积电的0.6微米SPDM CMOS工艺已设计出3.3V ADPLL芯片的原型。仿真表明，该nADPLL可以在60至400 MHz的范围内工作，并且工作频率是参考时钟频率的四倍。锁相过程需要47个时钟周期，并且相位误差小于0.1 ns

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《IEEE Transactions on Circuits and Systems. II, Express Briefs》 |1999年第7期|p.945-950|共6页
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Jen-Shiun Chiang; Kuang-Yuan Chen;
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1. The design of an all-digital phase-locked loop with small DCO hardware and fast phase lock [J] . Jen-Shiun Chiang, Kuang-Yuan Chen IEEE Transactions on Circuits and Systems. II . 1999,第7期

机译：具有小型DCO硬件和快速锁相功能的全数字锁相环的设计
2. A Design Procedure for All-Digital Phase-Locked Loops Based on a Charge-Pump Phase-Locked-Loop Analogy [J] . Kratyuk V., Hanumolu P.K., Un-Ku Moon, IEEE transactions on circuits and systems. II, Express briefs . 2007,第3期

机译：基于电荷泵锁相环类比的全数字锁相环设计程序
3. A Design Procedure for All-Digital Phase-Locked Loops Based on a Charge-Pump Phase-Locked-Loop Analogy [J] . Volodymyr Kratyuk, Pavan Kumar Hanumolu, Un-Ku Moon, IEEE Transactions on Circuits and Systems. II, Analog and Digital Signal Processing . 2007,第期

机译：基于电荷泵锁相环类比的全数字锁相环设计程序
4. An all-digital phase-locked loop with dynamic phase control for fast locking [C] . Chuang Yun-Chen, Tsai Sung-Lin, Liu Cheng-En, IEEE Asian Solid State Circuits Conference . 2012

机译：具有动态相位控制的全数字锁相环，可实现快速锁定
5. Research and design of low jitter, wide locking-range all-digital phase-locked and delay-locked loops. [D] . Lin, Feng. 2000

机译：低抖动，宽锁定范围全数字锁相环和延迟锁相环的研究和设计。
6. Quantitative comparison of wideband low-latency phase-locked loop circuit designs for high-speed frequency modulation atomic force microscopy [O] . Kazuki Miyata, Takeshi Fukuma 2018

机译：高速调频原子力显微镜的宽带低延迟锁相环电路设计的定量比较
7. A design procedure for all-digital phase-locked loops based on a charge-pump phase-locked-loop analogy [O] . Volodymyr Kratyuk, Student Member, Pavan Kumar Hanumolu, 2007

机译：基于电荷泵锁相环类比的全数字锁相环设计程序
8. Application of multirate digital filter banks to wideband all-digital phase-locked loops design [R] . Sadr, R., Shah, B., Hinedi, S. 1992

机译：多速率数字滤波器组在宽带全数字锁相环设计中的应用

The design of an all-digital phase-locked loop with small DCOhardware and fast phase lock

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