首页> 外文期刊>IEEE Transactions on Circuits and Systems for Video Technology >Cost-Effective Hardware-Sharing Design of Fast Algorithm Based Multiple Forward and Inverse Transforms for H.264/AVC, MPEG-1/2/4, AVS, and VC-1 Video Encoding and Decoding Applications
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Cost-Effective Hardware-Sharing Design of Fast Algorithm Based Multiple Forward and Inverse Transforms for H.264/AVC, MPEG-1/2/4, AVS, and VC-1 Video Encoding and Decoding Applications

机译:适用于H.264 / AVC,MPEG-1 / 2/4,AVS和VC-1视频编码和解码应用的基于快速算法的多重正反变换的经济高效的硬件共享设计

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摘要

In this letter, multiple forward and inverse fast algorithm based transforms and their hardware-sharing design for 2 $,times,$ 2, 4 $,times,$ 4, and 8 $,times,$ 8 transforms in H.264/AVC, and the 8 $,times,$ 8 transform in audio video coding standard, 4 $,times,$ 4 and 8 $,times,$ 8 transforms in VC-1, and DCT/IDCT in MPEG-1/2/4 are developed with a low hardware cost for multistandard video coding applications. Compared with the directly combined fast transforms without shares, the proposed low-cost 1-D architecture reduces shifters by 67%, adders by 73%, and gate counts by 53.4%. The hardware-sharing efficiencies of shifters and adders in the proposed 1-D transform design are 32% and 25% more than those in the previous design, respectively. By 0.18- $mu{rm m}$ CMOS technology, the proposed 2-D transform architecture has less normalized power per mode and larger normalized hardware efficiency than the previous multiple-standard designs. The cost-effective 2-D full pipelined transform achieves multistandard real-time 1080HD at 60-Hz video encoding and decoding applications.
机译:在这封信中,针对H.264 / AVC中2 $,2、4、4、8的多次正向和逆快速算法转换及其硬件共享设计,以及音频视频编码标准中的8 $ times $ 8转换,VC-1中的4 $ times,$ 4和8 $ times,$ 8转换以及MPEG-1 / 2/4中的DCT / IDCT针对多标准视频编码应用开发的硬件成本较低。与没有份额的直接组合快速变换相比,拟议的低成本一维架构可将移位器减少67%,将加法器减少73%,将门数减少53.4%。拟议的一维变换设计中的移位器和加法器的硬件共享效率分别比以前的设计高32%和25%。通过0.18-μmCMOS技术,与以前的多标准设计相比,所提出的2-D转换体系结构具有更低的每模规格化功率和更大的规格化硬件效率。具有成本效益的二维全流水线转换可在60 Hz视频编码和解码应用中实现多标准实时1080HD。

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