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首页> 外文期刊>Circuits, Devices & Systems, IET >Accelerating low-voltage SAR ADC operation via comparator timing assisted and circuit adaptive tuning techniques
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Accelerating low-voltage SAR ADC operation via comparator timing assisted and circuit adaptive tuning techniques

机译：通过比较器定时辅助和电路自适应调谐技术加速低压SAR ADC操作

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摘要

This work presents techniques that effectively utilise comparator timing information to accelerate low-voltage successive approximation register (SAR) analogue-to-digital converter (ADC) operation. Compared to existing approaches that only exploit the prolonged comparator decision time in the events of metastability, the proposed techniques are effective in a broader voltage range and can extract more information about the voltages being compared. To cope with large variations associated with comparator delay, this work proposes robust timing measurement circuit, uncertainty-tolerant search algorithm and circuit adaptive tuning techniques. The adaptive tuning technique enables ADC to autonomously find voltage levels corresponding to the outputs of the timing measurement circuit as well as to adjust the uncertainty ranges used in the search algorithm. This eliminates the need of post-silicon calibration for the timing measurement circuits, which are typically required in existing approaches. The developed techniques are used in the design of a 9-bit 0.45 V SAR ADC circuit with a 130 nm complementary metal-oxide-semiconductor technology. Measurement results from the prototype chip indicate that for most input levels the proposed ADC completes conversion in six or seven conversion cycles. At 200 KS/s sampling rate, its power dissipation is 2.88 mu W and it achieves a signal-to-noise distortion ratio of 50.66 dB with a figure of merit of 51.8 fJ/c.-s.
机译：该工作提供了有效利用比较器时序信息来加速低压连续近似寄存器（SAR）模拟到数字转换器（ADC）操作的技术。与现有方法相比，仅利用长时间的比较器决定时间在卷发性事件中，所提出的技术在更广泛的电压范围内有效，并且可以提取更多关于进行比较电压的信息。为了应对与比较器延迟相关的大变量，这项工作提出了稳健的时序测量电路，不确定性耐受搜索算法和电路自适应调谐技术。自适应调谐技术使ADC能够自主地找到与定时测量电路的输出对应的电压电平，以及调整搜索算法中使用的不确定性范围。这消除了针对定时测量电路的硅后校准的需要，这些电路通常是现有方法中的。开发技术用于设计具有130nm互补金属氧化物半导体技术的9位0.45V SAR ADC电路的设计。来自原型芯片的测量结果表明，对于大多数输入电平，所提出的ADC在六个或七个转换周期中完成转换。以200 ks / s的采样率，其功耗为2.88 mu w，它实现了50.66 dB的信号 - 噪声失真率，具有51.8 fj / c.-s的价值。

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