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首页> 外文期刊>Circuits, Devices & Systems, IET >Development of low-complexity all-digital frequency locked loop as 500 MHz reference clock generator for field-programmable gate array
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Development of low-complexity all-digital frequency locked loop as 500 MHz reference clock generator for field-programmable gate array

机译：低复杂度全数字锁频环作为500 MHz参考时钟发生器的开发，用于现场可编程门阵列

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摘要

The authors report the development of an on-chip 500 MHz reference clock generator as a part of a clock manager for a field-programmable gate array. The generator is implemented in the form of an all-digital frequency locked loop (ADFLL) in architecture of low complexity and high modularity. For the development of the ADFLL, they propose a new circuit that employs two under-sampled 1-bit 94;:3; frequency-to-digital converters to convert a frequency difference into a proportional distributed pulsewidth. By the combination of the proposed circuit with a conventional phase-and-frequency detector, a frequency comparator is implemented and can indicate its two input frequency conditions, that is, (i) equal to, (ii) lower than or (iii) higher than. The ADFLL which adopts the proposed frequency comparator is implemented in a 90 nm CMOS technology. Consuming 2.64 mW from a 1.2 V supply, the ADFLL shows about 50 ;C;s of locking time at the frequency accuracy of 99.2% while operating at 500 MHz and being driven by a 10 MHz reference clock.
机译：作者报告了作为现场可编程门阵列时钟管理器一部分的片上500 MHz参考时钟发生器的开发。该发生器以低复杂度和高模块化架构的全数字锁频环（ADFLL）形式实现。为了开发ADFLL，他们提出了一种采用两个欠采样1位94;：3;的新电路。频率数字转换器，将频率差转换为成比例的分布式脉冲宽度。通过将建议的电路与常规的相位和频率检测器组合，可以实现一个频率比较器，并可以指示其两个输入频率条件，即（i）等于，（ii）低于或（iii）高于比。采用建议的频率比较器的ADFLL采用90 nm CMOS技术实现。 ADFLL在1.2 V电源下消耗2.64 mW的功率，在500 MHz的频率下工作并由10 MHz的参考时钟驱动时，在99.2％的频率精度下显示约50 C的锁定时间。

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