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首页> 外文期刊>Circuits, systems and signal processing >Power- and Area-Optimized High-Level Synthesis Implementation of a Digital Down Converter for Software-Defined Radio Applications
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Power- and Area-Optimized High-Level Synthesis Implementation of a Digital Down Converter for Software-Defined Radio Applications

机译：用于软件定义的无线电应用的数字下变频器的功率和区域优化的高级合成实现

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摘要

In digital signal processing, digital down converters (DDCs) convert digitized, band-limited signals to lower frequency signals at a smaller sampling rate to simplify subsequent filtering stages. Software-defined radio (SDR) is a radio communication system in which components that are traditionally implemented in hardware are implemented in software on an embedded system. DDCs are widely used in modern communication systems, such as SDRs. Herein, we propose a low-power- and area-optimized implementation of a DDC for SDR applications. The DDC was designed using an innovative and novel high-level synthesis (HLS) design method based on application-specific bit widths for data nodes. The results achieved after a field programmable gate array (FPGA) implementation are superior to those obtained from hand-coded register transfer level (RTL) implementations in terms of area and power efficiency, with almost the same speed of operation. Our results were obtained using the MATLAB hardware description language (HDL) coder for HLS and Xilinx Vivado (a software for the synthesis and analysis of HDL designs) for synthesis. The DDC down-converts an input of 200 MHz signal to an output of 2 MHz signal. This implementation was conducted on a real FPGA hardware (Xilinx Kintex-7) and verified against the design specifications using an FPGA in the loop feature of HDL Verifier and MATLAB. In addition, we propose a generic methodology for improving the area, speed, and power for different application designs and HLS tools. The proposed methodology is also applicable to hand-coded RTL designs for any application.
机译：在数字信号处理中，数字向下转换器（DDC）将数字化的带限量信号转换为以较小的采样率以较小的采样率降低频率信号以简化后续过滤级。软件定义的无线电（SDR）是一种无线电通信系统，其中传统上以硬件实现的组件在嵌入式系统上以软件实现。 DDC广泛用于现代通信系统，例如SDR。在此，我们提出了用于SDR应用的DDC的低功耗和区域优化实现。 DDC是使用基于应用程序特定位宽度的创新和新颖的高级合成（HLS）设计方法来设计数据节点。在现场可编程门阵列（FPGA）实施之后实现的结果优于由面积和功率效率的手工编码寄存器传输电平（RTL）实现中获得的结果，其操作速度几乎相同。我们的结果是使用Matlab硬件描述语言（HDL）编码器获得HLS和Xilinx Vivado（一种用于合成和分析HDL设计的软件）的合成。 DDC向下转换200 MHz信号的输入到2 MHz信号的输出。该实现是在真正的FPGA硬件（Xilinx Kintex-7）上进行的，并在HDL验证程序和MATLAB的循环特征中使用FPGA来验证设计规范。此外，我们提出了一种通用方法，用于改善不同应用设计和HLS工具的区域，速度和功率。所提出的方法也适用于用于任何应用的手工编码的RTL设计。

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