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首页> 外文期刊>Circuits, systems, and signal processing >Hardware Design for VLSI Implementation of Acoustic Feedback Canceller in Hearing Aids
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Hardware Design for VLSI Implementation of Acoustic Feedback Canceller in Hearing Aids

机译：助听器中声反馈消除器的VLSI实现的硬件设计

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摘要

Acoustic feedback is one of the major issues associated with the hearing aid users which limits the maximum amount of gain available for amplification and degrades the sound quality. In this paper, partitioned time-domain block LMS (PTBLMS) algorithm is proposed for efficient hardware realization of acoustic feedback cancellers (AFCs) in hearing aids. A full-parallel and a folded structure is derived using the proposed PTBLMS algorithm. The folded structure utilizing the time multiplexing of convolution and correlation operation and performing them in one arithmetic unit enables better hardware utilization. A low-complexity design is employed for realization of power normalization unit (for calculating normalized convergence factor) which involves squaring and division operations. The theoretical analysis illustrates that the proposed AFC structures offer L times higher throughput rate and requires proportionately less hardware resource than the existing one where L is the block length. ASIC synthesis results reveal that the proposed folded structure involves nearly 79 less area-delay product and 86 less energy per sample compared to the existing structure.
机译：声反馈是与助听器用户相关的主要问题之一，它限制了可用于放大的最大增益量并降低了声音质量。本文提出了一种分区时域块LMS（PTBLMS）算法，用于助听器中声反馈消除器（AFC）的高效硬件实现。使用提出的PTBLMS算法，可以得出全平行和折叠结构。利用卷积和相关运算的时间多路复用并在一个算术单元中执行它们的折叠结构可以更好地利用硬件。一种低复杂度的设计用于实现功率归一化单元（用于计算归一化收敛因子），其中涉及平方和除法运算。理论分析表明，与现有的AFC结构（其中L是块长）相比，拟议的AFC结构提供了高出L倍的吞吐速率，并且所需的硬件资源也成比例地减少。 ASIC合成结果表明，与现有结构相比，拟议的折叠结构所涉及的单位面积积几乎减少了79％，每个样品的能量减少了86％。

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