High-Speed Digital Domino Logic for Ultra-Low Supply Voltages

Mirmotahari Omid; Berg Yngvar

首页> 外文期刊>Circuits, systems, and signal processing >High-Speed Digital Domino Logic for Ultra-Low Supply Voltages

【24h】

High-Speed Digital Domino Logic for Ultra-Low Supply Voltages

机译：用于超低电源电压的高速数字Domino逻辑

获取原文

获取原文并翻译 | 示例

掌桥外文数据库（机构版） >>

开具论文收录证明 >>

文献代查 >>

页面导航

摘要
著录项
相似文献
相关主题

摘要

We present a high-speed differential clocked voltage switch logic inverter operating at ultra-low supply voltages (ULV). Simulated data for the new gate are presented and compared to modified clocked voltage switch logic (CVSL). Preliminary measurements for ULV gates are presented. The increase in speed for supply voltages below 300 mV for the ULV gate presented is between 10 and 20 times compared to modified CVSL logic.

机译：我们提出了一种以超低电源电压（ULV）运行的高速差分时钟电压开关逻辑反相器。给出了新栅极的仿真数据，并将其与修改后的时钟电压开关逻辑（CVSL）进行比较。介绍了ULV门的初步测量。与修改后的CVSL逻辑相比，针对ULV门的电源电压低于300 mV的速度提高了10到20倍。

著录项

来源
《Circuits, systems, and signal processing》 |2017年第12期|4774-4788|共15页
作者
Mirmotahari Omid; Berg Yngvar;
展开▼
作者单位

Univ Oslo, Dept Informat, Nanoelect, Oslo, Norway;

Univ Oslo, Dept Informat, Nanoelect, Oslo, Norway;

展开▼
收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种 eng
中图分类
关键词
Low-voltage; Dynamic CMOS; High-speed; Differential; Dual-rail;

机译：低压;动态CMOS;高速;差分;双轨;

相似文献

外文文献
中文文献
专利

1. A Low Power High-Speed 8-Bit Pipelining CLA Design Using Dual-Threshold Voltage Domino Logic [J] . Wang C.-C., Huang C.-C., Lee C.-L., IEEE transactions on very large scale integration (VLSI) systems . 2008,第5期

机译：使用双阈值电压Domino逻辑的低功耗高速8位流水线CLA设计
2. A 1.5-V CMOS all-N-logic true-single-phase bootstrapped dynamic-logic circuit suitable for low supply voltage and high-speed pipelined system operation [J] . Lou J.H., Kuo J.B. IEEE Transactions on Circuits and Systems. II . 1999,第5期

机译：1.5V CMOS全N逻辑真单相自举动态逻辑电路，适合低电源电压和高速流水线系统操作
3. A high-speed low-power tri-state driver flip flop for ultra-low supply voltage GaAs heterojunction FET LSI's [J] . Maeda T., Numata K. IEEE Journal of Solid-State Circuits . 1996,第2期

机译：高速低功耗三态驱动器触发器，用于超低电源电压GaAs异质结FET LSI
4. Sub-Domino logic: ultra-low power dynamic sub-threshold digital logic [C] . Soeleman, H., Roy, . 2001

机译：子骨牌逻辑：超低功耗动态子阈值数字逻辑
5. Clock logic domino circuits for high-speed and energy efficient microprocessor pipelines [D] . Sung, Raymond Jit-Hung 2003

机译：用于高速和节能微处理器管线的时钟逻辑多米诺电路
6. Factors Influencing Difficulty of Laparoscopic Abdominoperineal Resection for Ultra-Low Rectal Cancer [O] . Qiken Li, Dechuan Li, Lai Jiang, -1

机译：影响超低位直肠癌腹腔镜腹部手术切除难度的因素
7. A Low Power High-Speed 8-Bit Pipelining CLA Design Using Dual-Threshold Voltage Domino Logic” ,In [O] . Chua-chin Wang, Senior Member, Chi-chun Huang, 2008

机译：采用双阈值电压Domino逻辑的低功耗高速8位流水线CLa设计“，In

High-Speed Digital Domino Logic for Ultra-Low Supply Voltages

摘要

著录项

相似文献

相关主题

期刊订阅