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Modified PEB Formulation for Hardware-Efficient Fixed-Width Booth Multiplier

机译：用于硬件的固定宽度展位乘法器的修改的PEB公式

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摘要

In this paper, we propose a modified probabilistic estimation bias (PEB) formula for fixed-width radix-4 Booth multiplier. The modified PEB formula estimates the same compensation value as the existing PEB formula without rounding operation. A bias circuit based on modified PEB formula generates one less carry-bit and involves less logic resources than the existing PEB circuit. The partial product array (PPA) of existing PEB multiplier uses partial product bit as guard bit for sign extension. This is not an efficient approach as extra half-adders (HAs) are required to accumulate these sign extension bits. We have considered PPA of conventional modified Booth encoded (MBE) multiplier where logic '1' is used as guard bit for sign extension. Logic '1' in the PPA helps to replace HA with a NOT-gate in the adder design. Based on the proposed scheme, we have derived an efficient adder design for PEB radix-4 Booth multiplier. Compared with the adder design of existing PEB multiplier, the proposed adder involves less logic resources and less critical path delay (CPD), and calculates the same compensation value. ASIC synthesis result shows that the proposed PEB radix-4 Booth multiplier of sizes n = 8, 10, 12, and 16, respectively, involves 18, 19, 16, and 13 % less area-delay product (ADP), and 12, 16, 11, and 12 % less power consumption than the existing PEB multiplier. We have shown that an inner-product (IP) cell based on proposed fixed-width radix-4 Booth multiplier involves 11.3% less ADP and consumes nearly 7.6 % less power than an IP cell based on the existing PEB-based fixed-width multiplier on average for different inner-product sizes. The proposed multiplier is, therefore, a useful component to develop high-performance systems for digital signal processing applications.
机译：在本文中，我们为固定宽度基数为4的Booth乘法器提出了一种改进的概率估计偏差（PEB）公式。修改后的PEB公式估算的补偿值与现有PEB公式相同，无需四舍五入运算。与现有的PEB电路相比，基于修改后的PEB公式的偏置电路生成的进位位数更少，所涉及的逻辑资源也更少。现有PEB乘法器的部分乘积数组（PPA）使用部分乘积位作为符号扩展的保护位。这不是一种有效的方法，因为需要额外的半加器（HA）来累积这些符号扩展位。我们已经考虑了常规修改的Booth编码（MBE）乘法器的PPA，其中逻辑“ 1”用作符号扩展的保护位。 PPA中的逻辑“ 1”有助于在加法器设计中用非门代替HA。基于提出的方案，我们推导了PEB radix-4 Booth乘法器的高效加法器设计。与现有PEB乘法器的加法器设计相比，该加法器所需的逻辑资源更少，关键路径延迟（CPD）更少，并且可以计算出相同的补偿值。 ASIC综合结果表明，建议的大小为n = 8、10、12和16的PEB radix-4 Booth乘数分别减少了18、19、16和13％的面积延迟乘积（ADP）和12与现有的PEB乘法器相比，功耗降低了16％，11％和12％。我们已经表明，与基于现有基于PEB的固定宽度乘数的IP单元相比，基于建议的固定宽度radix-4 Booth乘数的内部乘积（IP）单元的ADP减少了11.3％，功耗降低了近7.6％平均来说，对于不同的内产品尺寸。因此，提出的乘法器是开发用于数字信号处理应用的高性能系统的有用组件。

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