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首页> 外文期刊>Circuits and systems >Open Source Synthesis and Verification Tool for Fixed-to-Floating and Floating-to-Fixed Points Conversions
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Open Source Synthesis and Verification Tool for Fixed-to-Floating and Floating-to-Fixed Points Conversions

机译：开源的综合和验证工具，用于固定到浮动和浮动到固定点的转换

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摘要

An open source high level synthesis fixed-to-floating and floating-to-fixed conversion tool is presented for embedded design, communication systems, and signal processing applications. Many systems use a fixed point number system. Fixed point numbers often need to be converted to floating point numbers for higher accuracy, dynamic range, fixed-length transmission limitations or end user requirements. A similar conversion system is needed to convert floating point numbers to fixed point numbers due to the advantages that fixed point numbers offer when compared with floating point number systems, such as compact hardware, reduced verification time and design effort. The latest embedded and SoC designs use both number systems together to improve accuracy or reduce required hardware in the same design. The proposed open source design and verification tool converts fixed point numbers to floating point numbers, and floating point numbers to fixed point numbers using the IEEE-754 floating point number standard. This open source design tool generates HDL code and its test bench that can be implemented in FPGA and VLSI systems. The design can be compiled and simulated using open source Iverilog/GTKWave and verified using Octave. A high level synthesis tool and GUI are designed using C#. The proposed design tool can increase productivity by reducing the design and verification time, as well as reduce the development cost due to the open source nature of the design tool. The proposed design tool can be used as a standalone block generator or implemented into current designs to improve range, accuracy, and reduce the development cost. The generated design has been implemented on Xilinx FPGAs.
机译：提出了一种用于嵌入式设计，通信系统和信号处理应用的开源高级综合固定到浮动和浮动到固定转换工具。许多系统使用定点数字系统。为了获得更高的精度，动态范围，固定长度的传输限制或最终用户要求，通常需要将定点数转换为浮点数。由于定点数与浮点数系统相比具有优势，例如紧凑的硬件，减少的验证时间和设计工作，因此需要类似的转换系统将浮点数转换为定点数。最新的嵌入式和SoC设计将两种数字系统一起使用，以提高精度或减少同一设计中所需的硬件。拟议的开源设计和验证工具使用IEEE-754浮点数标准将定点数转换为浮点数，并将浮点数转换为定点数。该开源设计工具生成可在FPGA和VLSI系统中实现的HDL代码及其测试平台。可以使用开源Iverilog / GTKWave编译和仿真设计，并使用Octave进行验证。使用C＃设计了高级综合工具和GUI。所提出的设计工具可以通过减少设计和验证时间来提高生产率，并且由于设计工具的开源性质而可以降低开发成本。所提出的设计工具可以用作独立的块生成器，也可以实现为当前的设计，以提高范围，精度并降低开发成本。生成的设计已在Xilinx FPGA上实现。

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  • 来源
    《Circuits and systems》 |2016年第11期|3874-3885|共12页
  • 作者

    Semih Aslan; Ekram Mohammad; Azim Hassan Salamy;

  • 作者单位

    Ingram School of Engineering, Electrical Engineering Texas State University, San Marcos, Texas, USA;

    Ingram School of Engineering, Electrical Engineering Texas State University, San Marcos, Texas, USA;

    School of Engineering, Electrical Engineering University of St. Thomas, St. Paul, Minnesota, USA;

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  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

    FPGA; VLSI; RTL; Iverilog; GTKWave; OCTAVE; HLS; C#; Open Source;

    机译：FPGA;超大规模集成电路RTL;Iverilog;GTKWave;八度;HLS;C＃;开源的;

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