A Subthreshold Low-Voltage Low-Phase-Noise CMOS LC-VCO with Resistive Biasing

Jungnam Bae; Saichandrateja Radhapuram; Ikkyun Jo; Takao Kihara; Toshimasa Matsuoka

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A Subthreshold Low-Voltage Low-Phase-Noise CMOS LC-VCO with Resistive Biasing

机译：具有电阻偏置的亚阈值低电压，低相位噪声CMOS LC-VCO

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摘要

This paper presents a low-phase-noise LC voltage-controlled oscillator (LC-VCO) with top resistive biasing in subthreshold region. The subthreshold LC-VCO has low-power and low-phase-noise due to its high transconductance efficiency and low gate bias condition. The top resistive biasing has more benefit with the feature of phase noise than MOS current source since it can support the low-noise characteristics and large output swing. The LC-VCO designed in 130-nm CMOS process with 0.7-V supply voltage achieves phase noise of -116 dBc/Hz at 200 kHz offset with tuning range of 398 MHz to 408 MHz covering medical implant communication service (MICS) band.

机译：本文提出了一种在亚阈值区域具有顶部电阻偏置的低相位噪声LC压控振荡器（LC-VCO）。亚阈值LC-VCO由于具有高跨导效率和低栅极偏置条件，因此具有低功耗和低相位噪声的特性。顶部电阻偏置比MOS电流源具有更多的相位噪声特性，因为它可以支持低噪声特性和大输出摆幅。具有130V CMOS工艺，0.7V电源电压的LC-VCO在200 kHz偏移下的相位噪声为-116 dBc / Hz，调谐范围为398 MHz至408 MHz，覆盖医疗植入物通信服务（MICS）频段。

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来源
《Circuits and systems》 |2015年第5期|136-142|共7页
作者
Jungnam Bae; Saichandrateja Radhapuram; Ikkyun Jo; Takao Kihara; Toshimasa Matsuoka;
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作者单位

Graduate School of Engineering, Osaka University, Osaka, Japan;

Graduate School of Engineering, Osaka University, Osaka, Japan;

Graduate School of Engineering, Osaka University, Osaka, Japan;

Faculty of Engineering, Osaka Institute of Technology, Osaka, Japan;

Graduate School of Engineering, Osaka University, Osaka, Japan;

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原文格式 PDF
正文语种 eng
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关键词
VCO; Resistive Biasing; Current Source; CMOS Integrated Circuit; Phase Noise; MICS Band;

机译：VCO;电阻偏置电流源;CMOS集成电路相位噪声MICS乐队;

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专利

1. A Subthreshold Low-Voltage Low-Phase-Noise CMOS LC-VCO with Resistive Biasing [J] . Jungnam Bae, Saichandrateja Radhapuram, Ikkyun Jo, Circuits and Systems . 2015,第5期

机译：具有电阻偏置的亚阈值低电压，低相位噪声CMOS LC-VCO
2. A 2.4 GHz high-linearity low-phase-noise CMOS LC-VCO based on capacitance compensation [J] . Li Zhenrong, Zhuang Yiqi, Li Bing, Journal of Semiconductors . 2010,第7期

机译：基于电容补偿的2.4 GHz高线性度低相位噪声CMOS LC-VCO
3. 5.18-7.42 GHz LC-VCO in subthreshold regime with low power low phase noise and immunity to PVT variations in 130 nm CMOS technology [J] . Aitoumeri Abdelhamid, Bouyahyaoui Abdelmalik, Alami Mustapha Analog Integrated Circuits and Signal Processing . 2018,第1期

机译：5.18-7.42 GHz LC-VCO，亚阈值制度，低功耗低相位噪声和130nm CMOS技术的PVT变化的免疫力
4. Compact sub-milliwatt low-phase-noise CMOS LC-VCO based on power reduction technique [C] . Jung J., Upadhyaya P., Liu P., 2011 IEEE MTT-S International Microwave Symposium Digest . 2011

机译：基于功率降低技术的紧凑型亚兆瓦低相噪CMOS LC-VCO
5. A new architecture for low-voltage low-phase-noise high-frequency CMOS LC voltage-controlled oscillator. [D] . Lieu, Anthony D. 2005

机译：低压低相位噪声高频CMOS LC压控振荡器的新架构。
6. Low-Voltage 96 dB Snapshot CMOS Image Sensor with 4.5 nW Power Dissipation per Pixel [O] . Arthur Spivak, Adam Teman, Alexander Belenky, 2012

机译：低压96 dB快照CMOS图像传感器每像素功耗4.5 nW
7. A Subthreshold Low-Voltage Low-Phase-Noise CMOS LC-VCO with Resistive Biasing [O] . Bae Jungnam, Radhapuram Saichandrateja, Jo Ikkyun, 2015

机译：具有电阻偏置的亚阈值低电压，低相位噪声CMOS LC-VCO

A Subthreshold Low-Voltage Low-Phase-Noise CMOS LC-VCO with Resistive Biasing

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