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New Hybrid Digital Circuit Design Techniques for Reducing Subthreshold Leakage Power in Standby Mode

机译：降低待机模式下亚阈值泄漏功率的新型混合数字电路设计技术

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摘要

In this paper, four new hybrid digital circuit design techniques, namely, hybrid multi-threshold CMOS complete stack technique, hybrid multi-threshold CMOS partial stack technique, hybrid super cutoff complete stack technique and hybrid super cutoff partial stack technique, have been proposed to reduce the subthreshold leakage power dissipation in standby modes. Techniques available in literature are compared with our proposed hybrid circuit design techniques. Performance parameters such as subthreshold leakage power dissipation in active and standby modes, dynamic power dissipation and propagation delay, are compared using existing and proposed hybrid techniques for a two input AND gate. Reduction of subthreshold leakage power dissipation in standby mode is given more importance, in comparison with the other circuit design performance parameters. It is found that there is reduction in subthreshold leakage power dissipation in standby and active modes by 3.5× and 1.15× respectively using the proposed hybrid super cutoff complete stack technique as compared to the existing multi-threshold CMOS (MTCMOS) technique. Also a saving of 2.50× and 1.04× in subthreshold leakage power dissipation in standby and active modes respectively were observed using hybrid super cutoff complete stack technique as compared to the existing super cutoff CMOS (SCCMOS) technique. The proposed hybrid super cutoff stack technique proved to perform better in terms of subthreshold leakage power dissipation in standby mode in comparison with other techniques. Simulation results using Microwind EDA tool in 65 nm CMOS technology is provided in this paper.
机译：本文提出了四种新的混合数字电路设计技术，即混合多阈值CMOS完全堆叠技术，混合多阈值CMOS部分堆叠技术，混合超级截止全堆叠技术和混合超级截止局部堆叠技术。降低待机模式下的亚阈值泄漏功耗。将文献中可用的技术与我们提出的混合电路设计技术进行了比较。使用现有和建议的混合技术对两个输入“与”门进行比较，比较性能参数，例如在活动和待机模式下的亚阈值泄漏功耗，动态功耗和传播延迟。与其他电路设计性能参数相比，降低待机模式下阈值泄漏功耗的重要性更高。结果发现，与现有的多阈值CMOS（MTCMOS）技术相比，使用拟议的混合超级截止完全堆叠技术，待机和活动模式下的亚阈值泄漏功耗分别降低了3.5倍和1.15倍。与现有的超级截止CMOS（SCCMOS）技术相比，使用混合超级截止完全堆叠技术在待机和活动模式下的亚阈值泄漏功耗分别节省了2.50倍和1.04倍。与其他技术相比，所提出的混合超级截止堆技术在待机模式下的亚阈值泄漏功率耗散方面表现出更好的性能。本文提供了使用Microwind EDA工具和65 nm CMOS技术进行的仿真结果。

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