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New Analysis to Measure the Capacitance and Conductance of MOS Structure toward Small Size of VLSI Circuits

机译:测量小尺寸VLSI电路MOS结构的电容和电导的新分析

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In this research thin film layers have been prepared at alternate layers of resistive and dielectric deposited on appropriate substrates to form four - terminal R-Y-NR network. If the gate of the MOS structures deposited as a strip of resistor film like NiCr, the MOS structure can be analyzed as R-Y-NR network. A method of analysis has been proposed to measure the shunt capacitance and the shunt conductance of certain MOS samples. Mat lab program has been used to compute shunt capacitance and shunt conductance at different frequencies. The results computed by this method have been compared with the results obtained by LCR meter method and showed perfect coincident with each other.
机译:在这项研究中,在电阻和电介质的交替层上制备了薄膜层,该层沉积在适当的基板上以形成四端R-Y-NR网络。如果将MOS结构的栅极沉积为像NiCr这样的电阻膜带,则可以将MOS结构分析为R-Y-NR网络。提出了一种分析方法来测量某些MOS样品的并联电容和并联电导。 Mat lab程序已用于计算不同频率下的并联电容和并联电导。通过该方法计算出的结果已与通过LCR仪表方法获得的结果进行了比较,并且显示出彼此完全一致。

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