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首页> 外文期刊>Components, Packaging and Manufacturing Technology, IEEE Transactions on >Development of a Cu/Low-$k$ Stack Die Fine Pitch Ball Grid Array (FBGA) Package for System in Package Applications
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Development of a Cu/Low-$k$ Stack Die Fine Pitch Ball Grid Array (FBGA) Package for System in Package Applications

机译：用于封装应用系统的铜/低-k $叠层模细间距球栅阵列（FBGA）封装的开发

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摘要

Consumers' demands have driven the industry toward devices and packages with low cost, high performance, and multiple functions. Stacking two or more chips into one package becomes a popular choice. In this paper, the development of a three-die stack fine pitch ball grid array package is reported. A 65 nm Cu/low- $k$ die is used as the bottom die in the package to increase the speed of the chip with multilayer interconnect structures. Compared to the conventional dielectrics, low-$k$ materials are softer and less resistant to thermal-mechanical stress induced by packaging processes. In this paper, finite element analysis is performed to minimize the stress in low-$k$ layers and to address the low-$k$ delamination issue. In the dicing evaluation, comparison among straight cut, bevel cut and two-step cut was performed in terms of die strength and chipping results. It is found that the bevel cut dicing method is the best dicing method. The die attach process (especially wire embedded film process) is optimized to ensure that no voids are present in the die attach materials after the bonding process. The ultralow loop wire bonding process (50 $mu{rm m}$) is also well established. The maximum wire sweep for all test vehicles is less than 10% in the molding process. Finally, all samples for test vehicle 1 were shown to have successfully passed JEDEC component level tests such as thermal cycling for 1000 cycles (${-}{rm 40}^{circ}{rm C}$ to 125$^{circ}{rm C}$) and high temperature storage (HTS at 150$^{circ}{rm C}$) for 1000 h.
机译：消费者的需求已将行业推向低成本，高性能和多功能的设备和包装。将两个或多个芯片堆叠成一个封装成为一种流行的选择。本文报道了三管芯细间距球栅阵列封装的开发。 65 nm Cu / low-k $裸片用作封装中的底部裸片，以提高具有多层互连结构的芯片的速度。与传统的电介质相比，低k $的材料更柔软，并且更难以抵抗封装过程中产生的热机械应力。在本文中，进行了有限元分析以最小化低$ k $层中的应力并解决低$ k $分层问题。在划片评价中，在模头强度和崩落结果方面进行了直切，斜切和两步切割之间的比较。发现斜切方法是最好的切割方法。优化了芯片附着工艺（特别是金属丝嵌入薄膜工艺），以确保在键合过程之后，芯片附着材料中不存在空隙。超低环线键合工艺（50μm{rm m} $）也很成熟。在成型过程中，所有测试车辆的最大扫线率均小于10％。最终，测试车辆1的所有样品均已成功通过JEDEC组件级测试，例如热循环1000次（$ {-} {rm 40} ^ {circ} {rm C} $至125 $ ^ {circ} {rm C} $）和高温存储（HTS在150 $ ^ {circ} {rm C} $）存储1000小时。

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