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首页> 外文期刊>Computer architecture news >Inspection Resistant Memory: Architectural Support for Security from Physical Examination
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Inspection Resistant Memory: Architectural Support for Security from Physical Examination

机译：抗检查内存：从物理检查获得安全性的体系结构支持

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摘要

The ability to safely keep a secret in memory is central to the vast majority of security schemes, but storing and erasing these secrets is a difficult problem in the face of an attacker who can obtain unrestricted physical access to the underlying hardware. Depending on the memory technology, the very act of storing a 1 instead of a 0 can have physical side effects measurable even after the power has been cut. These effects cannot be hidden easily, and if the secret stored on chip is of sufficient value, an attacker may go to extraordinary means to learn even a few bits of that information. Solving this problem requires a new class of architectures that measurably increase the difficulty of physical analysis. In this paper we take a first step towards this goal by focusing on one of the backbones of any hardware system: on-chip memory. We examine the relationship between security, area, and efficiency in these architectures, and quantitatively examine the resulting systems through cryptographic analysis and microarchitectural impact. In the end, we are able to find an efficient scheme in which, even if an adversary is able to inspect the value of a stored bit with a probabilistic error of only 5%, our system will be able to prevent that adversary from learning any information about the original un-coded bits with 99.9999999999% probability.
机译：安全地在内存中保留秘密的能力是绝大多数安全方案的核心，但是面对攻击者，他们可以获得对底层硬件的不受限制的物理访问，因此存储和清除这些秘密是一个难题。根据存储技术的不同，存储1而不是0的行为即使在断电之后也可以测量到物理上的副作用。这些影响无法轻易隐藏，而且如果存储在芯片上的秘密具有足够的价值，攻击者可能会采取特殊的手段来学习甚至很少的信息。解决这个问题需要一类新的架构，可观地增加了物理分析的难度。在本文中，我们通过着重于任何硬件系统的骨干之一：片上存储器，朝着这一目标迈出了第一步。我们检查了这些体系结构中安全性，面积和效率之间的关系，并通过密码分析和微体系结构影响定量地检查了所得系统。最后，我们能够找到一种有效的方案，即使对手能够以仅5％的概率误差检查存储的位的值，我们的系统也能够防止该对手学习任何有关原始未编码位的信息，概率为99.9999999999％。

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