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首页> 外文期刊>Computers and Artificial Intelligence >AN INTERPROCESSOR COMMUNICATION INTERFACE FOR MESSAGE PASSING VIA SHARED MEMORY MODULES - DESIGN AND PERFORMANCES
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AN INTERPROCESSOR COMMUNICATION INTERFACE FOR MESSAGE PASSING VIA SHARED MEMORY MODULES - DESIGN AND PERFORMANCES

机译：通过共享内存模块进行消息传递的处理器间通信接口-设计和性能

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In this paper the interprocessor communication interface intended for realization of multi-microcomputer (MMC) system is described. The MMC system is implemented as a Fully_Connected_n-sidd_Pyramid (FCnP). The base of the pyramid consists of n processors and it acts as an accelerator to the host computer that is placed at the top of the pyramid. Communication between any two processor takes place through Shared_Memory_Module (SMM) independently accessed by both processors involved in current data transfer. The SMMs are realized with two-side accessible memory chips of FIFO RAM type. For the processors we use standard Single_Board_Computers (SBC) extended with a communication hardware referred to as the Communication-Module (CM). The main task of the CM is to provide efficient DMA data transfer between the SBC′s local memory and SMMs. Attaching the CM to the SBC requires only some minor modification of the SBC′s hardware. In order to connect one SBC with several SMMs a special bus named Shared-Memory_Bus (SMB), is provided. Higher FCnP′s performances, in comparison with the common bus based MMC systems, are obtained mainly due to: increased communication bandwidth, possibility to use heterogeneous processors, and configuration flexibility of system topology. This paper deals with hardware structure of constituent parts of the communication interface (CM, SMM, and SMB), and system operation concerning the message transfer. Further on, performance evaluation for the proposed communication interface related to system efficiency, communication throughput, and message latency are carried out. Simulation analysis is also included.
机译：在本文中，描述了用于实现多微计算机（MMC）系统的处理器间通信接口。 MMC系统被实现为Fully_Connected_n-sidd_Pyramid（FCnP）。金字塔的底部由n个处理器组成，它充当位于金字塔顶部的主机的加速器。任何两个处理器之间的通信都是通过Shared_Memory_Module（SMM）进行的，由参与当前数据传输的两个处理器独立访问。 SMM通过FIFO RAM类型的两侧可访问存储芯片来实现。对于处理器，我们使用标准的Single_Board_Computers（SBC）扩展了通信硬件，称为通信模块（CM）。 CM的主要任务是在SBC的本地内存和SMM之间提供有效的DMA数据传输。将CM连接到SBC只需对SBC的硬件进行一些小改动即可。为了将一个SBC与多个SMM连接，提供了一个名为Shared-Memory_Bus（SMB）的特殊总线。与基于公共总线的MMC系统相比，获得更高的FCnP性能的主要原因是：通信带宽增加，使用异构处理器的可能性以及系统拓扑的配置灵活性。本文讨论了通信接口（CM，SMM和SMB）组成部分的硬件结构，以及与消息传输有关的系统操作。进一步地，针对与系统效率，通信吞吐量和消息等待时间有关的所提议的通信接口执行性能评估。还包括仿真分析。

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