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Hardware Division by Small Integer Constants

机译：小整数常量的硬件划分

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This article studies the design of custom circuits for division by a small positive constant. Such circuits can be useful for specific FPGA and ASIC applications. The first problem studied is the Euclidean division of an unsigned integer by a constant, computing a quotient and remainder. Several new solutions are proposed and compared against the state-of-the-art. As the proposed solutions use small look-up tables, they match well with the hardware resources of an FPGA. The article then studies whether the division by the product of two constants is better implemented as two successive dividers or as one atomic divider. It also considers the case when only a quotient or only a remainder is needed. Finally, it addresses the correct rounding of the division of a floating-point number by a small integer constant. All these solutions, and the previous state-of-the-art, are compared in terms of timing, area, and area-timing product. In general, the relevance domains of the various techniques are different on FPGA and on ASIC.
机译：本文研究了定制电路的设计，以将其除以一个小的正常数。这样的电路对于特定的FPGA和ASIC应用可能有用。研究的第一个问题是无符号整数的欧几里德除以常数，计算出商和余数。提出了几种新的解决方案，并与最新技术进行了比较。由于建议的解决方案使用小的查找表，因此它们与FPGA的硬件资源非常匹配。然后，本文研究将两个常数的乘积除以更好的方式实现为两个连续的除法器还是一个原子除法器。它还考虑仅需要商或仅需要余数的情况。最后，它解决了将浮点数除以小整数常量的正确舍入方法。所有这些解决方案以及以前的最新技术都在时序，面积和面积定时产品方面进行了比较。通常，各种技术的相关域在FPGA和ASIC上是不同的。

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