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One Attack to Rule Them All: Collision Timing Attack versus 42 AES ASIC Cores

机译：一种攻击来统治所有人：冲突定时攻击与42个AES ASIC内核

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摘要

When complex functions, for example, substitution boxes of block ciphers, are realized in hardware, timing attributes of the underlying combinational circuit depend on the input/output changes of the function. These characteristics can be exploited by the help of a relatively new scheme called fault sensitivity analysis. A collision timing attack which exploits the data-dependent timing characteristics of combinational circuits is demonstrated in this paper. The attack is based on an also recently published correlation collision attack, which avoids the need for a hypothetical timing model for the underlying combinational circuit to recover the secret materials. The target platforms of our proposed attack are 14 AES ASIC cores of the SASEBO LSI chips in three different process technologies, 13 nm, 90 nm, and 65 nm. Successfully breaking all cores including the DPA-protected and fault attack protected cores indicates the strength of the attack.
机译：当在硬件中实现复杂功能（例如块密码的替换盒）时，基础组合电路的时序属性取决于功能的输入/输出变化。这些特性可以通过称为故障敏感性分析的相对较新的方案来利用。本文展示了一种利用组合电路的数据相关时序特征进行的碰撞时序攻击。该攻击基于最近还发布的相关冲突攻击，它避免了底层组合电路为恢复秘密材料而需要的假设时序模型。我们提出的攻击的目标平台是SASEBO LSI芯片的14个AES ASIC内核，采用三种不同的处理技术：13 nm，90 nm和65 nm。成功中断所有内核，包括受DPA保护的内核和受故障攻击保护的内核，表明攻击的强度。

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