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首页> 外文期刊>Computers, IEEE Transactions on >A Low Hardware Overhead Self-Diagnosis Technique Using Reed-Solomon Codes for Self-Repairing Chips
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A Low Hardware Overhead Self-Diagnosis Technique Using Reed-Solomon Codes for Self-Repairing Chips

机译：使用Reed-Solomon码的自修复芯片的低硬件开销自诊断技术

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摘要

A self-diagnosis circuit that can be used for built-in self-repair is proposed. The circuit under diagnosis is assumed to be composed of a large number of field repairable units (FRUs), which can be replaced with spares when they are found to be defective. Since the proposed self-diagnosis circuit is implemented on the chip, responses that are scanned out of scan chains are compressed by the group compactor, the space compression circuit, and finally, the time compression circuit to reduce the volume of test response data. Both the space and time compression circuits implement a Reed-Solomon code. Unlike prior work, in the proposed technique, responses of all FRUs are observed at the same time to reduce diagnosis time. The proposed diagnosis circuit can locate up to l defective FRUs. We propose a novel space compression circuit that reduces hardware overhead by exploiting the frequency difference of the scan shift clock and the system clock and by combining scan cells into groups of size r. When the size of constituent multiple-input signature register (MISR) is m, the total number of signatures to be stored for the fault-free signature is 2lmB bits, where 1le B le m. The experimental results show that the proposed diagnosis circuit that can locate up to four defective FRUs in the same test session can be implemented with less than one percent of hardware overhead for a large industrial design. Hardware overhead for the diagnosis circuit is lower for large CUDs.
机译：提出了一种可用于内置自修复的自诊断电路。假定正在诊断的电路由大量的现场可修复单元（FRU）组成，当发现它们有故障时，可以用备件进行替换。由于所提出的自诊断电路是在芯片上实现的，因此从扫描链中扫描出来的响应将由组压缩器，空间压缩电路以及时间压缩电路压缩，以减少测试响应数据的数量。空间和时间压缩电路均实现了Reed-Solomon码。与先前的工作不同，在提出的技术中，同时观察所有FRU的响应以减少诊断时间。建议的诊断电路最多可以定位1个有故障的FRU。我们提出了一种新颖的空间压缩电路，该电路可通过利用扫描移位时钟和系统时钟的频率差并将扫描单元合并为大小为r的组来减少硬件开销。当组成的多输入签名寄存器（MISR）的大小为m时，要为无故障签名存储的签名总数为2lmB位，其中1le B le m。实验结果表明，针对大型工业设计，所提出的诊断电路可以在同一测试会话中最多定位四个有缺陷的FRU，而硬件开销却不到百分之一。对于大型CUD，诊断电路的硬件开销较低。

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