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Power-performance simulation and design strategies for single-chip heterogeneous multiprocessors

机译：单芯片异构多处理器的功率性能仿真和设计策略

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Single chip heterogeneous multiprocessors (SCHMs) are becoming more commonplace, especially in portable devices where reduced energy consumption is a priority. The use of coordinated collections of processors which are simpler or which execute at lower clock frequencies is widely recognized as a means of reducing power while maintaining latency and throughput. A primary limitation of using this approach to reduce power at the system level has been the time to develop and simulate models of many processors at the instruction set simulator level. High-level models, simulators, and design strategies for SCHMs are required to enable designers to think in terms of collections of cooperating, heterogeneous processors in order to reduce power. Toward this end, this paper has two contributions. The first is to extend a unique, preexisting high-level performance simulator, the Modeling Environment for Software and Hardware (MESH), to include power annotations. MESH can be thought of as a thread-level simulator instead of an instruction-level simulator. Thus, the problem is to understand how power might be calibrated and annotated with program fragments instead of at the instruction level. Program fragments are finer-grained than threads and coarser-grained than instructions. Our experimentation found that compilers produce instruction patterns that allow power to be annotated at this level using a single number over all compiler-generated fragments executing on a processor. Since energy is power*time, this makes system runtime (i.e., performance) the dominant factor to be dynamically calculated at this level of simulation. The second contribution arises from the observation that high-level modeling is most beneficial when it opens up new possibilities for organizing designs. Thus, we introduce a design strategy, enabled by the high-level performance power-simulation, which we refer to as spatial voltage scaling. The strategy both reduces overall system power consumption and improves performance in our example. The design space for this design strategy could not be explored without high-level SCHM power-performance simulation.
机译：单芯片异构多处理器（SCHM）变得越来越普遍，尤其是在优先考虑降低能耗的便携式设备中。使用更简单或以较低时钟频率执行的处理器的协调集合被广泛认为是在保持等待时间和吞吐量的同时降低功耗的一种手段。使用这种方法在系统级别降低功耗的主要限制是在指令集模拟器级别开发和仿真许多处理器的模型的时间。需要SCHM的高级模型，仿真器和设计策略，以使设计人员能够考虑协作的异构处理器的集合，以降低功耗。为此，本文有两个贡献。首先是扩展一个独特的，预先存在的高级性能模拟器，即软件和硬件建模环境（MESH），以包含电源注释。可以将MESH视为线程级模拟器，而不是指令级模拟器。因此，问题是要了解如何用程序片段而不是在指令级别上对功率进行校准和注释。程序片段比线程更细粒度，指令比更粗粒度。我们的实验发现，编译器产生的指令模式允许在处理器上执行的所有编译器生成的片段上使用单个数字在此级别注释功率。由于能量是功率*时间，因此这使得系统运行时间（即性能）成为在此模拟级别上动态计算的主要因素。第二个贡献来自以下观察：高级建模在为组织设计提供新的可能性时最有利。因此，我们介绍了一种由高级性能功耗仿真实现的设计策略，我们将其称为空间电压缩放。在我们的示例中，该策略既减少了总体系统功耗，又提高了性能。没有高级SCHM功率性能仿真，就无法探索该设计策略的设计空间。

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