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首页> 外文期刊>IEEE Transactions on Computers >Simulation and generation of IDDQ tests for bridging faults in combinational circuits
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Simulation and generation of IDDQ tests for bridging faults in combinational circuits

机译:组合电路中桥接故障的IDDQ测试的仿真和生成

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摘要

In the absence of information about the layout, test generation and fault simulation systems must target all bridging faults. A novel algorithm, that is both time and space efficient, for simulating I/sub DDQ/ tests for all two-line bridging faults in combinational circuits is presented. Simulation results using randomly generated test sets point to the computational feasibility of targeting all two-line bridging faults. On a more theoretical note, we show that the problem of computing I/sub DDQ/ tests for all two-line bridging faults, even in some restricted classes of circuits, is intractable, and, even under some pessimistic assumptions, a complete I/sub DDQ/ test set for all two-line bridging faults also covers all multiple line, single cluster bridging faults.
机译:在缺乏有关布局的信息的情况下,测试生成和故障模拟系统必须针对所有桥接故障。提出了一种既节省时间又节省空间的新颖算法,用于模拟组合电路中所有两线桥接故障的I / sub DDQ /测试。使用随机生成的测试集的仿真结果表明,针对所有两线桥接故障的计算可行性。从理论上讲,我们表明,即使在某些受限的电路类别中,为所有两线桥接故障计算I / sub DDQ /测试的问题也是棘手的,即使在某些悲观的假设下,完整的I /所有两线桥接故障的子DDQ /测试集也涵盖了所有多线,单群集桥接故障。

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