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首页> 外文期刊>American journal of applied sciences >HARDWARE MODELING OF BINARY CODED DECIMAL ADDER IN FIELD PROGRAMMABLE GATE ARRAY | Science Publications
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HARDWARE MODELING OF BINARY CODED DECIMAL ADDER IN FIELD PROGRAMMABLE GATE ARRAY | Science Publications

机译：现场可编程门阵列中二进制编码十进制加法器的硬件建模科学出版物

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摘要

> There are insignificant relevant research works available which are involved with the Field Programmable Gate Array (FPGA) based hardware implementation of Binary Coded Decimal (BCD) adder. This is because, the FPGA based hardware realization is quiet new and still developing field of research. The article illustrates the design and hardware modeling of a BCD adder. Among the types of adders, Carry Look Ahead (CLA) and Ripple Carry (RC) adder have been studied, designed and compared in terms of area consumption and time requirement. The simulation results show that the CLA adder performs faster with optimized area consumption. Verilog Hardware Description Language (HDL) is used for designing the model with the help of Altera Quartus II Electronic Design Automation (EDA) tool. EDA synthesis tools make it easy to develop an HDL model and which can be synthesized into target-specific architectures. Whereas, the HDL based modeling provides shorter development phases with continuous testing and verification of the system performance and behavior. After successful functional and timing simulations of the CLA based BCD adder, the design has been downloaded to physical FPGA device. For FPGA implementation, the Altera DE2 board has been used which contains Altera Cyclone II 2C35 FPGA device.
机译： >目前，与基于二进制编码十进制（BCD）加法器的基于现场可编程门阵列（FPGA）的硬件实现有关的相关研究工作微不足道。这是因为，基于FPGA的硬件实现是一个安静而又新的研究领域。本文说明了BCD加法器的设计和硬件建模。在加法器类型中，已经研究，设计和比较了随身携带（CLA）和纹波随身携带（RC）加法器的面积消耗和时间要求。仿真结果表明，CLA加法器的性能更快，且面积消耗最佳。 Verilog硬件描述语言（HDL）用于借助Altera Quartus II电子设计自动化（EDA）工具来设计模型。 EDA综合工具使开发HDL模型变得容易，并且可以将其综合到特定于目标的体系结构中。鉴于基于HDL的建模提供了更短的开发阶段，可以对系统性能和行为进行连续测试和验证。在成功完成了基于CLA的BCD加法器的功能和时序仿真后，该设计已下载到物理FPGA器件。对于FPGA实施，已使用Altera DE2板，其中包含Altera Cyclone II 2C35 FPGA器件。

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