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首页> 外文期刊>International Journal of Computer Network and Information Security >Implementation of An Optimized and Pipelined Combinational Logic Rijndael S-Box on FPGA
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Implementation of An Optimized and Pipelined Combinational Logic Rijndael S-Box on FPGA

机译：优化的流水线组合逻辑Rijndael S-Box在FPGA上的实现

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摘要

In this paper, presents an optimized combinational logic based Rijndael S-Box implementation for the SubByte transformation(S-box) in the Advanced Encryption Standard (AES) algorithm on FPGA. S-box dominated the hardware complexity of the AES cryptographic module thus we implement its mathematic equations based on optimized and combinational logic circuits until dynamic power consumption reduced. The complete data path of the S-box algorithm is simulated as a net list of AND, OR, NOT and XOR logic gates, also for increase in speed and maximum operation frequency used 4-stage pipeline in proposed method. The proposed implemented combinational logic based S-box have been successfully synthesized and implemented using Xilinx ISE V7.1 and Virtex IV FPGA to target device Xc4vf100. Power is analized using Xilinx XPower analyzer and achieved power consumption is 29 mW in clock frequency of 100 MHz. The results from the Place and Route report indicate that maximum clock frequency is 209.617 MHz.
机译：本文针对FPGA上的高级加密标准（AES）算法中的SubByte变换（S-box），提出了一种基于优化组合逻辑的Rijndael S-Box实现。 S-box主导了AES密码模块的硬件复杂性，因此我们基于优化和组合逻辑电路来实现其数学方程式，直到降低动态功耗为止。 S-box算法的完整数据路径被模拟为AND，OR，NOT和XOR逻辑门的网表，也为提高速度和最大工作频率而使用了4级流水线。拟议的已实现的基于组合逻辑的S-box已成功使用Xilinx ISE V7.1和Virtex IV FPGA进行了综合，并以Xc4vf100为目标器件。使用Xilinx XPower分析仪对电源进行了分析，在100 MHz的时钟频率下实现的功耗为29 mW。 “放置和布线”报告的结果表明，最大时钟频率为209.617 MHz。

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