...
首页> 外文期刊>International Journal of Engineering Trends and Technology >Speed and Area optimized Design of DDR3 SDRAM (Double Data Rate3 Synchronously Dynamic RAM) Controller for Digital TV Decoders
【24h】

Speed and Area optimized Design of DDR3 SDRAM (Double Data Rate3 Synchronously Dynamic RAM) Controller for Digital TV Decoders

机译:用于数字电视解码器的DDR3 SDRAM(双倍数据速率3同步动态RAM)控制器的速度和面积优化设计

获取原文
           

摘要

Today to store large amount of data generally so many memory devices are availablein the market. But to access the storage data a need of retrieval devices should be needed. Inthis paper to accommodate that type of task a DDR3SDRAM IS PROPOSED. The proposedmemory design is modeled using finite state machine which should be used in the internalblock of setup box application. To maintain the functionality different FIFO’s and counterdesign are included in the proposed architecture. For each block HDL code is developed basedon VERILOG language. In this paper the Xilinx ISE EDA Tool is used for synthesis andModelsim is used for simulation.
机译:如今,通常要存储大量数据,因此市场上有许多存储设备可用。但是,要访问存储数据,需要检索设备。为了适应这种任务,本文提出了DDR3SDRAM。所提出的存储器设计使用有限状态机进行建模,该状态机应在设置盒应用程序的内部模块中使用。为了保持功能,建议的体系结构中包含了不同的FIFO和计数器设计。对于每个块,HDL代码都是基于VERILOG语言开发的。本文使用Xilinx ISE EDA工具进行综合,使用Modelsim进行仿真。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号