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首页> 外文期刊>International Journal of Engineering Science and Technology >DESIGN OF VOLTAGE CONTROLLED DELAY LINE FOR WIDE FREQUENCY RANGE WITH LOW POWER DISSIPATION
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DESIGN OF VOLTAGE CONTROLLED DELAY LINE FOR WIDE FREQUENCY RANGE WITH LOW POWER DISSIPATION

机译：低功耗宽频率范围的电压控制延迟线设计

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Voltage controlled delay line is most important component in Delay Locked Loop (DLL).The Delay line is formed by connecting number of delay cells with a delay ranging from several picoseconds to nanoseconds. As the operating frequency range increases, the power dissipation in DLL also increases causing serious issues like false locking problem. By changing the control voltage in delay line, the delay and power dissipation in DLL can be reduced. The delay line is designed by different CMOS logic families. For a Low supply voltage and High frequency range of operation, the delay line structure can be obtained by using a current starved delay cell or differential delay cell using CML. The design of delay line structure using CML offers less number of transistors leading to small area. It can also be used in both analog and digital delay locked loops. The proposed delay lines structure shows that by increasing the frequency range, the power dissipation and delay are reduced. This circuit is designed by Mentor Graphics Tools using 130nm technology.
机译：电压控制延迟线是延迟锁定环（DLL）中最重要的组件。延迟线是通过连接多个延迟单元而形成的，延迟单元的延迟范围从几皮秒到十亿微秒。随着工作频率范围的增加，DLL中的功耗也会增加，从而导致严重的问题，例如错误锁定问题。通过更改延迟线中的控制电压，可以减少DLL中的延迟和功耗。延迟线由不同的CMOS逻辑系列设计。对于低电源电压和高工作频率范围，可以通过使用电流不足的延迟单元或使用CML的差分延迟单元来获得延迟线结构。使用CML的延迟线结构设计减少了晶体管的数量，从而减小了面积。它也可以在模拟和数字延迟锁定环路中使用。所提出的延迟线结构表明，通过增加频率范围，可以降低功耗和延迟。该电路是由Mentor Graphics Tools使用130nm技术设计的。

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