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首页> 外文期刊>International Journal of Power Electronics and Drive Systems >Investigation of the Common Mode Voltage for a Neutral-Point-Clamped Multilevel Inverter Drive and its Innovative Elimination through SVPWM Switching-State Redundancy
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Investigation of the Common Mode Voltage for a Neutral-Point-Clamped Multilevel Inverter Drive and its Innovative Elimination through SVPWM Switching-State Redundancy

机译：中点钳位多电平逆变器驱动的共模电压研究及其通过SVPWM开关状态冗余的创新消除

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摘要

The purpose of this paper is to provide a comprehensive Investigations and its control on the common mode Voltage (CMV) of the three-phase three-level neutral-point diode-clamped (NPC) multilevel inverter (MLI). A widespread space-vector pulse width modulation (SVPWM) technique to mitigate the perpetual problem of the NPC-MLI, the CMV, proposed. The proposed scheme is an effectual blend of nearest three vector (NTV) and selected three vector (STV) techniques. This scheme is capable to reduce the CMV without compromise the inverter output voltage and Total harmonics distraction (THD). CMV reduction achieved less than +Vdc/6 using the proposed vector selection procedure. The theoretical Investigations, the MATLAB software based computer simulation and Field Programmable Gate Array (FPGA) supported hardware corroboration have shown the superiority of the proposed technique over the conventional SVPWM schemes.
机译：本文的目的是对三相三电平中性点二极管钳位（NPC）多电平逆变器（MLI）的共模电压（CMV）进行全面的研究及其控制。提出了一种广泛的空间矢量脉冲宽度调制（SVPWM）技术，以缓解NPC-MLI（CMV）的永久性问题。所提出的方案是最近三个向量（NTV）和选定的三个向量（STV）技术的有效融合。该方案能够降低CMV，而不会影响逆变器的输出电压和总谐波干扰（THD）。使用建议的向量选择程序，CMV减少量小于+ Vdc / 6。理论研究，基于MATLAB软件的计算机仿真和现场可编程门阵列（FPGA）支持的硬件确证表明，所提出的技术优于传统的SVPWM方案。

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