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首页> 外文期刊>EURASIP journal on advances in signal processing >Real-time parallel implementation of Pulse-Doppler radar signal processing chain on a massively parallel machine based on multi-core DSP and Serial RapidIO interconnect
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Real-time parallel implementation of Pulse-Doppler radar signal processing chain on a massively parallel machine based on multi-core DSP and Serial RapidIO interconnect

机译：基于多核DSP和串行RapidIO互连的大规模并行机上脉冲多普勒雷达信号处理链的实时并行实现

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摘要

Pulse-Doppler radars require high-computing power. A massively parallel machine has been developed in this paper to implement a Pulse-Doppler radar signal processing chain in real-time fashion. The proposed machine consists of two C6678 digital signal processors (DSPs), each with eight DSP cores, interconnected with Serial RapidIO (SRIO) bus. In this study, each individual core is considered as the basic processing element; hence, the proposed parallel machine contains 16 processing elements. A straightforward model has been adopted to distribute the Pulse-Doppler radar signal processing chain. This model provides low latency, but communication inefficiency limits system performance. This paper proposes several optimizations that greatly reduce the inter-processor communication in a straightforward model and improves the parallel efficiency of the system. A use case of the Pulse-Doppler radar signal processing chain has been used to illustrate and validate the concept of the proposed mapping model. Experimental results show that the parallel efficiency of the proposed parallel machine is about 90%.
机译：脉冲多普勒雷达需要高计算能力。本文开发了一种大规模并行机，以实时方式实现脉冲多普勒雷达信号处理链。拟议中的机器包括两个C6678数字信号处理器（DSP），每个具有八个DSP内核，并与串行RapidIO（SRIO）总线互连。在这项研究中，每个核心都被视为基本处理元素。因此，建议的并行机包含16个处理元素。采用了一个简单的模型来分配脉冲多普勒雷达信号处理链。该模型提供了低延迟，但是通信效率低下限制了系统性能。本文提出了几种优化方法，这些优化方法可以大大减少直接模型中的处理器间通信，并提高系统的并行效率。脉冲多普勒雷达信号处理链的一个用例已被用来说明和验证所提出的映射模型的概念。实验结果表明，所提出的并行机的并行效率约为90％。

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