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首页> 外文期刊>Nanoscience and Nanoengineering >Effect of Nanowire-dielectric Interface on the Hysteresis of Solution Processed Silicon Nanowire FETs
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Effect of Nanowire-dielectric Interface on the Hysteresis of Solution Processed Silicon Nanowire FETs

机译：纳米线-介电界面对溶液处理的硅纳米线FET的磁滞的影响

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Silicon nanowires (Si NW) are ideal candidates for low-cost solution processed field effect transistors (FETs) due to the ability of nanowires to be dispersed in solvents, and demonstrated high charge carrier mobility. The interface between the nanowire and the dielectric plays a crucial role in the FET characteristics, and can be responsible for unwanted effects such as current hysteresis during device operation. Thus, optimal nanowire- dielectric interface is required for low-hysteresis FET performance. Here we show that NW FET hysteresis mostly depends on the nature of the dielectric material by directly comparing device characteristics of dual gate Si NW FETs with bottom SiO2 gate dielectric and top hydrophobic fluoropolymer gate dielectric. As the transistor semiconducting nanowire channel is identical in both tops and bottom operational regimes, the performance differences originate from the nature of the nanowire-dielectric interface. Thus, very high 30 volt hysteresis is observed for forward and reverse gate bias scans with SiO2 interface; however, hysteresis is significantly reduced to 6 volt for the fluoropolymer dielectric interface. The differences in hysteresis are ascribed to the polar OH- groups present at SiO2/Si nanowire interface, and mostly absent at fluoropolymer/Si nanowire interface. We further demonstrate that high density of charge traps for bottom gate SiO2 interface (1× 1013cm-2) is reduced by over an order of magnitude for top-fluoropolymer gate interface (7.5 × 1011 cm-2), therefore highlighting the advantage of hydrophobic polymer gate dielectrics for nanowire field-effect transistor applications.
机译：硅纳米线（Si NW）由于可以分散在溶剂中，并且具有高的载流子迁移率，因此是低成本溶液处理场效应晶体管（FET）的理想选择。纳米线和电介质之间的界面在FET特性中起着至关重要的作用，并且可能导致器件运行期间产生不良影响，例如电流滞后。因此，低滞后FET性能需要最佳的纳米线-介电界面。在这里，我们通过直接比较具有底部SiO 2 栅极电介质和顶部疏水性含氟聚合物栅极电介质的双栅极Si NW FET的器件特性，表明NW FET磁滞主要取决于电介质材料的性质。由于晶体管半导体纳米线通道的顶部和底部操作方式均相同，因此性能差异源自纳米线-电介质界面的性质。因此，对于具有SiO 2 界面的正向和反向栅极偏置扫描，观察到非常高的30伏滞回。然而，对于含氟聚合物介电界面，磁滞明显降低至6伏。磁滞的差异归因于存在于SiO 2 / Si纳米线界面上的极性OH-基团，而在含氟聚合物/ Si纳米线界面上几乎不存在。我们进一步证明，底栅SiO 2 界面（1×10 13 cm -2 ）的高电荷陷阱密度降低了顶部含氟聚合物栅界面的数量级为（7.5×10 11 cm -2 ），因此突出了疏水聚合物栅介质在纳米线场效应晶体管应用中的优势。

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