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首页> 外文期刊>Nonlinear Theory and Its Applications >A CMOS circuit for PWM-mode nonlinear transformation robust to device mismatches to implement coupled map lattice models
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A CMOS circuit for PWM-mode nonlinear transformation robust to device mismatches to implement coupled map lattice models

机译：用于对器件失配具有鲁棒性的PWM模式非线性变换的CMOS电路，以实现耦合的图格模型

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摘要

In order to develop large-scale nonlinear dynamical systems using CMOS integrated circuits, we propose a core circuit for coupled map lattice (CML) models. The characteristics of the core circuits in the lattice on a chip are not generally equal, which is caused by CMOS device mismatches, including parasitic capacitance and wiring resistance. The proposed circuit solves this problem; it compensates for a DC offset voltage variation by holding it at a capacitor, and also for current variation by adjusting the bias voltage of a current source automatically so as to bring the current close to a target value. The proposed core circuit has been designed and fabricated using TSMC 0.25 μm CMOS technology. The measurement results using the fabricated circuit have shown that the bit precision is more than 8 bits, even if there is a DC offset voltage of 100 mV or a bias-voltage change of 100 mV in a switched current source.
机译：为了开发使用CMOS集成电路的大规模非线性动力学系统，我们提出了一种用于耦合映射晶格（CML）模型的核心电路。芯片上晶格中核心电路的特性通常不相等，这是由CMOS器件不匹配（包括寄生电容和布线电阻）引起的。拟议的电路解决了这个问题。它通过将其保持在电容器上来补偿DC偏移电压变化，并通过自动调节电流源的偏置电压以使电流接近目标值来补偿电流变化。所建议的核心电路是使用TSMC 0.25μmCMOS技术设计和制造的。使用装配好的电路的测量结果表明，即使在开关电流源中存在100 mV的DC偏移电压或100 mV的偏置电压变化，位精度也超过8位。

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