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首页> 外文期刊>Turkish Journal of Electrical Engineering and Computer Sciences >Design of a low-power CMOS operational amplifier with common-mode feedback for pipeline analog-to-digital converter applications
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Design of a low-power CMOS operational amplifier with common-mode feedback for pipeline analog-to-digital converter applications

机译：具有流水线模数转换器应用的具有共模反馈的低功耗CMOS运算放大器的设计

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摘要

This paper proposes a design of a low-power operational amplifier (op-amp) for pipeline analog-to-digital converter (ADC) applications using a 0.13-$mu $m CMOS process. The folded-cascode topology with NMOS input types is employed for the op-amp design due to a larger output gain compared to PMOS input types. Furthermore, the op-amp is designed with a double detection structure of a common-mode feedback circuit to provide stable feedback voltage. The simulation results show that the proposed op-amp achieved a gain of 64.5 dB and a unity gain bandwidth of 695.1 MHz with a low power consumption of 0.14 mW. In addition, by applying $pm $1.2 V of input voltage, the output voltage generated by the proposed op-amp design remains at 1.2 V with a constant feedback voltage of 1.3 V. Moreover, the proposed circuit was implemented and simulated successfully in a 1.5-bit per stage pipeline ADC.
机译：本文提出了一种采用0.13μmCMOS工艺的流水线模数转换器（ADC）应用的低功耗运算放大器（op-amp）设计。具有NMOS输入类型的折叠共源共栅拓扑被用于运算放大器设计，因为与PMOS输入类型相比，它具有更大的输出增益。此外，该运算放大器设计有共模反馈电路的双重检测结构，以提供稳定的反馈电压。仿真结果表明，所提出的运算放大器实现了64.5 dB的增益和695.1 MHz的单位增益带宽，且功耗仅为0.14 mW。另外，通过施加$ pm $ 1.2 V的输入电压，所提出的运算放大器设计产生的输出电压保持在1.2 V，恒定反馈电压为1.3V。此外，所提出的电路在A每级1.5位流水线ADC。

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