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首页> 外文期刊>Journal of Low Power Electronics and Applications >Error Detection and Recovery Techniques for Variation-Aware CMOS Computing: A Comprehensive Review †
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Error Detection and Recovery Techniques for Variation-Aware CMOS Computing: A Comprehensive Review †

机译:用于变体感知CMOS计算的错误检测和恢复技术:全面综述†

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While Moore's law scaling continues to double transistor density every technology generation, new design challenges are introduced. One of these challenges is variation, resulting in deviations in the behavior of transistors, most importantly in switching delays. These exaggerated delays widen the gap between the average and the worst case behavior of a circuit. Conventionally, circuits are designed to accommodate the worst case delay and are therefore becoming very limited in their performance advantages. Thus, allowing for an average case oriented design is a promising solution, maintaining the pace of performance improvement over future generations. However, to maintain correctness, such an approach will require on the fly mechanisms to prevent, detect, and resolve violations. This paper explores such mechanisms, allowing the improvement of circuit performance under intensifying variations. We present speculative error detection techniques along with recovery mechanisms. We continue by discussing their ability to operate under extreme variations including sub-threshold operation. While the main focus of this survey is on circuit approaches, for its completeness, we discuss higher-level, architectural and algorithmic techniques as well.
机译:尽管摩尔定律定标在每一代技术中都继续使晶体管密度增加一倍,但也带来了新的设计挑战。这些挑战之一是变化,导致晶体管性能的偏差,最重要的是开关延迟。这些夸大的延迟扩大了电路的平均行为与最坏情况之间的差距。常规上,电路被设计为适应最坏情况下的延迟,因此其性能优势变得非常有限。因此,允许以平均情况为导向的设计是一种有前途的解决方案,可以保持性能提升的步伐。但是,为了保持正确性,这种方法将需要动态机制来防止,检测和解决违规情况。本文探讨了这种机制,可以在不断变化的情况下改善电路性能。我们介绍了推测性错误检测技术以及恢复机制。我们将继续讨论它们在极端变化(包括亚阈值运行)下的运行能力。尽管此调查的主要重点是电路方法,但出于完整性考虑,我们还将讨论更高级别的体系结构和算法技术。

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