FPGA IMPLEMENTATION OF COEFFICIENT DECIMATED POLYPHASE FILTER BANK STRUCTURE FOR MULTISTANDARD COMMUNICATION RECEIVER

P. KALPANA DEVI; R. S. BHUVANESHWARAN

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FPGA IMPLEMENTATION OF COEFFICIENT DECIMATED POLYPHASE FILTER BANK STRUCTURE FOR MULTISTANDARD COMMUNICATION RECEIVER

机译：多标准通信接收器的高精度十进制多相滤波器组结构的FPGA实现

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Coefficient decimated polyphase FIR filter bank structure implemented for receiving narrow band channels effectively in multistandard environment. Reonfigurability in multirate filtering is required to design a prototype filter bank structure for selectin

机译：为在多标准环境中有效接收窄带信道而实施的系数抽取多相FIR滤波器组结构。设计用于selectin的原型滤波器组结构需要多速率滤波的可重构性

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《Journal of Theoretical and Applied Information Technology》 |2014年第2期|共页
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P. KALPANA DEVI; R. S. BHUVANESHWARAN;
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中图分类计算技术、计算机技术;
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1. FPGA IMPLEMENTATION OF COEFFICIENT DECIMATED POLYPHASE FILTER BANK STRUCTURE FOR MULTISTANDARD COMMUNICATION RECEIVER [J] . P. KALPANA DEVI, R. S. BHUVANESHWARAN Journal of Theoretical and Applied Information Technology . 2014,第2期

机译：多标准通信接收器的高精度十进制多相滤波器组结构的FPGA实现
2. Design of Reconfigurable Filter Bank Architecture Using Improved Coefficient Decimation-Interpolation-Masking Technique for Multi-Standard Wireless Communication Receivers [J] . Sumedh Dhabu, K. G. Smitha, A. P. Vinod Journal of Low Power Electronics . 2014,第3期

机译：多标准无线通信接收机中采用改进系数抽取插值掩盖技术的可重构滤波器组架构设计
3. 3-D IIR filtering using decimated DFT-polyphase filter bank structures [J] . Kuenzle B., Bruton L.T. IEEE transactions on circuits and systems . I , Regular papers . 2006,第2期

机译：使用抽取DFT多相滤波器组结构的3-D IIR滤波
4. Low Power FPGA-Based Implementation Of Decimating Filters For Multistandard Receiver [C] . Nadia Khouja, Khaled Grati, Adel Ghazel International Conference on Design and Test Integrated Systems . 2006

机译：基于低功耗FPGA的多标准接收器的抽取过滤器实现
5. Three-dimensional IIR filtering using decimated DFT-polyphase filter bank structures. [D] . Kuenzle, Bernhard. 2005

机译：使用抽取DFT多相滤波器组结构的三维IIR滤波。
6. Fast Convolution Filter-Bank Based Non-Orthogonal Multiplexed Cognitive Radio (NOMCR) Receiver Design Using Cyclostationarity Based FRESH Filtering [O] . Jayanta Datta, Hsin-Piao Lin 2018

机译：基于基于循环平稳性的FRESH滤波的基于快速卷积滤波器组的非正交多路复用认知无线电（NOMCR）接收器设计
7. FPGA Implementation of High Speed Reconfigurable Filter Bank for Multi-standard Wireless Communication Receivers [O] . Garg, Sasha, Darak, S. J. 2016

机译：FpGa高速可重构滤波器组的FpGa实现多标准无线通信接收器

FPGA IMPLEMENTATION OF COEFFICIENT DECIMATED POLYPHASE FILTER BANK STRUCTURE FOR MULTISTANDARD COMMUNICATION RECEIVER

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